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Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

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ATmega128 datasheet.pdf

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ATmega128

Two-wire Serial Interface Characteristics

Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 154.

Table 133. Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.3 VCC

VIH

Input High-voltage

0.7 VCC

VCC + 0.5

(1)

Hysteresis of Schmitt Trigger Inputs

(2)

–

Vhys

0.05 VCC

(1)

Output Low-voltage

3mA sink current

0.4

(1)

Rise Time for both SDA and SCL

20 + 0.1C

(3)(2)

300

(1)

Output Fall Time from V

IHmin

to V

ILmax

10pF < C < 400pF(3)

20 + 0.1C

(3)(2)

250

tSP(1)

Spikes Suppressed by Input Filter

50(2)

Input Current each I/O Pin

0.1 VCC < Vi < 0.9 VCC

-10

µA

(1)

Capacitance for each I/O Pin

–

SCL

SCL Clock Frequency

(4) > max(16f

, 250kHz)(5)

400

kHz

SCL

fSCL ≤ 100kHz

VCC – 0.4V

1000ns

----------------------------

-------------------

Value of Pull-up resistor

3mA

fSCL > 100kHz

VCC – 0.4V

300ns

----------------------------

---------------

3mA

tHD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100kHz

4.0

–

fSCL > 100kHz

0.6

–

tLOW

Low Period of the SCL Clock

fSCL ≤ 100kHz

4.7

–

fSCL > 100kHz

1.3

–

tHIGH

High period of the SCL clock

fSCL ≤ 100kHz

4.0

–

µs

fSCL > 100kHz

0.6

–

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100kHz

4.7

–

fSCL > 100kHz

0.6

–

tHD;DAT

Data hold time

fSCL ≤ 100kHz

3.45

fSCL > 100kHz

0.9

tSU;DAT

Data setup time

fSCL ≤ 100kHz

250

–

fSCL > 100kHz

100

–

tSU;STO

Setup time for STOP condition

fSCL ≤ 100kHz

4.0

–

fSCL > 100kHz

0.6

–

µs

tBUF

Bus free time between a STOP and START

fSCL ≤ 100kHz

4.7

–

condition

Notes: 1.

In ATmega128, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency

322

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ATmega128

5.This requirement applies to all Atmel® AVR® ATmega128 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

Figure 154. Two-wire Serial Bus Timing

tof

tHIGH

SCL

tLOW

tSU;STA

tHD;STA

tHD;DAT

SDA

SU;DAT

tSU;STO

tBUF

SPI Timing

Characteristics

See Figure 155 and Figure 156 for details.

Table 134. SPI Timing Parameters

Description

Mode

Min

Typ

Max

SCK period

Master

See Table 72

SCK high/low

Master

50% duty cycle

Rise/Fall time

Master

3.6

Setup

Master

Hold

Master

Out to SCK

Master

0.5 • tsck

SCK to out

Master

SCK to out high

Master

SS low to out

Slave

SCK period

Slave

4 • tck

SCK high/low(1)

Slave

2 • t

Rise/Fall time

Slave

1.6

µs

Setup

Slave

Hold

Slave

SCK to out

Slave

SCK to

high

Slave

high to tri-state

Slave

low to SCK

Slave

2 • tck

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

-2 tCLCL for fCK < 12MHz

-3 tCLCL for fCK >12MHz

323

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ATmega128

Figure 155. SPI Interface Timing Requirements (Master Mode)

SCK (CPOL = 0)

SCK (CPOL = 1)

MISO

(Data Input)

MOSI

(Data Output)

6			1
		2	2
4	5		3
	MSB	...	LSB
		7	8
	MSB	...	LSB

Figure 156. SPI Interface Timing Requirements (Slave Mode)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(Data Input)

MISO

(Data Output)

18
9			10	16
9
		11	11
13	14			12
	MSB	...	LSB
		15		17
	MSB	...	LSB	X

324

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ATmega128

ADC Characteristics

Table 135. ADC Characteristics, Single Ended Channels

Symbol	Parameter	Condition	Min(1)	Typ(1)	Max(1)	Units
	Resolution	Single Ended Conversion			10	Bits

		Single Ended Conversion
		VREF = 4V, VCC = 4V		1.5
		ADC clock = 200kHz

		Single Ended Conversion
		VREF = 4V, VCC = 4V		3.25
	Absolute Accuracy	ADC clock = 1MHz

		Single Ended Conversion
	(Including INL, DNL, Quantization Error, Gain	Single Ended Conversion
	(Including INL, DNL, Quantization Error, Gain	VREF = 4V, VCC = 4V
	and Offset Error)	VREF = 4V, VCC = 4V		1.5
	and Offset Error)	ADC clock = 200kHz		1.5
		ADC clock = 200kHz
		Noise Reduction mode

		Single Ended Conversion
		VREF = 4V, VCC = 4V		3.75
		ADC clock = 1MHz		3.75
		ADC clock = 1MHz				LSB
		Noise Reduction mode				LSB
		Noise Reduction mode

		Single Ended Conversion
	Integral Non-Linearity (INL)	VREF = 4V, VCC = 4V		0.75
		ADC clock = 200kHz

		Single Ended Conversion
	Differential Non-Linearity (DNL)	VREF = 4V, VCC = 4V		0.5
		ADC clock = 200kHz

		Single Ended Conversion
	Gain Error	VREF = 4V, VCC = 4V		1
		ADC clock = 200kHz

		Single Ended Conversion
	Offset error	VREF = 4V, VCC = 4V		1
		ADC clock = 200kHz

	Clock Frequency		50		1000	kHz

	Conversion Time		13		260	µs

AVCC	Analog Supply Voltage		VCC - 0.3(2)		VCC + 0.3(3)
VREF	Reference Voltage		2.0		AVCC	V
VIN	Input Voltage		GND		VREF
	Input Bandwidth				38.5	kHz

VINT	Internal Voltage Reference		2.3	2.56	2.7	V
RREF	Reference Input Resistance			32		kΩ
RAIN	Analog Input Resistance		55	100		MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V

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Table 136. ADC Characteristics, Differential Channels

Symbol	Parameter	Condition		Min(1)	Typ(1)	Max(1)	Units
		Gain =	1x			10

	Resolution	Gain =	10x			10	Bits

		Gain = 200x				10

		Gain = 1x
		VREF = 4V, VCC = 5V			17
		ADC clock = 50 - 200kHz

		Gain = 10x
	Absolute Accuracy	VREF = 4V, VCC = 5V			17
		ADC clock = 50 - 200kHz

		Gain = 200x
		VREF = 4V, VCC = 5V			7
		ADC clock = 50 - 200kHz					LSB

		Gain = 1x
		Gain = 1x
		VREF = 4V, VCC = 5V			1.5
		ADC clock = 50 - 200kHz
	Integral Non-Linearity (INL)
	Integral Non-Linearity (INL)	Gain = 10x
	(Accuracy after Calibration for Offset and	VREF = 4V, VCC = 5V			2
	Gain Error)	ADC clock = 50 - 200kHz

		Gain = 200x
		VREF = 4V, VCC = 5V			5
		ADC clock = 50 - 200kHz

		Gain =	1x		1.5

	Gain Error	Gain =	10x		1.5		%

		Gain = 200x			0.5

		Gain = 1x
		VREF = 4V, VCC = 5V			2
		ADC clock = 50 - 200kHz

		Gain = 10x
	Offset Error	VREF = 4V, VCC = 5V			3		LSB
		ADC clock = 50 - 200kHz

		Gain = 200x
		VREF = 4V, VCC = 5V			4
		ADC clock = 50 - 200kHz

	Clock Frequency			50		200	kHz

	Conversion Time			65		260	µs

AVCC	Analog Supply Voltage			VCC - 0.3(2)		VCC + 0.3(3)
VREF	Reference Voltage			2.0		AVCC - 0.5	V
VIN	Input Voltage			GND		VCC	V
VIN	Input Voltage			GND		VCC
VDIFF	Input Differential Voltage			-VREF/Gain		VREF/Gain
	ADC Conversion Output			-511		511	LSB

	Input Bandwidth				4		kHz

326

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ATmega128

Table 136. ADC Characteristics, Differential Channels (Continued)

Symbol	Parameter	Condition	Min(1)	Typ(1)	Max(1)	Units
VINT	Internal Voltage Reference		2.3	2.56	2.7	V
RREF	Reference Input Resistance			32		kΩ
RAIN	Analog Input Resistance		55	100		MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V.

327

2467X–AVR–06/11

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