
- •1 Features
- •2 Applications
- •3 Description
- •Table of Contents
- •4 Revision History
- •5 Pin Configuration and Functions
- •6 Specifications
- •6.1 Absolute Maximum Ratings
- •6.2 ESD Ratings
- •6.3 Recommended Operating Conditions
- •6.4 Thermal Information
- •6.5 Electrical Characteristics
- •6.6 Switching Characteristics
- •6.7 Operating Characteristics
- •6.8 Typical Characteristics
- •7 Parameter Measurement Information
- •8 Detailed Description
- •8.1 Overview
- •8.2 Functional Block Diagram
- •8.3 Feature Description
- •8.4 Device Functional Modes
- •9 Application and Implementation
- •9.1 Application Information
- •9.2 Typical Application
- •9.2.1 Design Requirements
- •9.2.2 Detailed Design Procedure
- •9.2.3 Application Curve
- •10 Power Supply Recommendations
- •11 Layout
- •11.1 Layout Guidelines
- •11.2 Layout Example
- •12 Device and Documentation Support
- •12.1 Documentation Support
- •12.1.1 Related Documentation
- •12.2 Community Resources
- •12.3 Trademarks
- •12.4 Electrostatic Discharge Caution
- •12.5 Glossary
- •13 Mechanical, Packaging, and Orderable Information

SN74AHCT1G08
www.ti.com |
SCLS315Q –MARCH 1996–REVISED APRIL 2016 |
8 Detailed Description
8.1 Overview
The SN74AHCT1G08 device is a single 2-input positive-AND gate. The device performs the Boolean AND function (Y = A • B or Y = A + B) in positive logic. Low ICC current allows this device to be used in powersensitive or battery-powered applications. Robust inputs allow the device to up-translate with a propagation delay of 20 ns.
8.2 Functional Block Diagram
A |
1 |
|
|
|
|
|
4 |
Y |
|||
2 |
|||||
B |
|
|
|||
|
|
||||
|
|
|
|||
|
|
|
|
||
|
|
|
|
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The VCC for the device is optimized at 5 V.
Up voltage translation from 3.3 V to 5 V is allowed. The inputs accept VIH levels of 2 V. Output ringing is minimized by slow edge rates.
Inputs are TTL-Voltage compatible.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AHCT1G08.
Table 1. Function Table
|
INPUTS |
OUTPUT |
|
A |
|
B |
Y |
H |
|
H |
H |
L |
|
X |
L |
X |
|
L |
L |
Copyright © 1996–2016, Texas Instruments Incorporated |
Submit Documentation Feedback |
7 |
Product Folder Links: SN74AHCT1G08