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PIC18F8722 FAMILY

18.4.3PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations:

Single Output

Half-Bridge Output

Full-Bridge Output, Forward mode

Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM mode discussed in Section 18.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow.

The general relationship of the outputs in all configurations is summarized in Figure 18-2.

FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

 

 

0

Duty

PR2 + 1

CCP1CON<7:6>

SIGNAL

 

Cycle

 

 

 

 

 

 

 

 

Period

 

00

(Single Output)

P1A Modulated

 

 

 

 

Delay(1)

Delay(1)

 

 

 

P1A Modulated

 

 

10

(Half-Bridge)

P1B Modulated

 

 

 

 

P1A Active

 

 

01

(Full-Bridge,

P1B Inactive

 

 

Forward)

 

 

 

 

 

P1C Inactive

 

 

 

 

P1D Modulated

 

 

 

 

P1A Inactive

 

 

11

(Full-Bridge,

P1B Modulated

 

 

Reverse)

 

 

 

 

P1C Active

 

 

 

 

 

 

 

 

P1D Inactive

 

 

Relationships:

 

 

 

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

 

 

• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

 

• Delay = 4 * TOSC * (ECCP1DEL<6:0>)

 

 

Note

1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable

 

Dead-Band Delay”).

 

 

DS39646B-page 194

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

 

 

0

Duty

PR2 + 1

 

CCP1CON<7:6>

SIGNAL

 

 

Cycle

 

 

 

 

 

 

 

 

Period

 

00

(Single Output)

P1A Modulated

 

 

 

 

P1A Modulated

Delay(1)

 

10

(Half-Bridge)

Delay(1)

 

P1B Modulated

 

 

 

 

P1A Active

 

 

01

(Full-Bridge,

P1B Inactive

 

 

Forward)

 

 

 

 

 

P1C Inactive

 

 

 

 

P1D Modulated

 

 

 

 

P1A Inactive

 

 

11

(Full-Bridge,

P1B Modulated

 

 

 

 

 

Reverse)

 

 

 

 

P1C Active

 

 

 

 

 

 

 

 

P1D Inactive

 

 

Relationships:

 

 

 

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

 

 

• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

 

• Delay = 4 * TOSC * (ECCP1DEL<6:0>)

 

 

Note

1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable

 

Dead-Band Delay”).

 

 

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 195

PIC18F8722 FAMILY

18.4.4HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge applications, as shown in Figure 18-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals.

In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, P1DC6:P1DC0 sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 18.4.6 “Programmable Dead-Band Delay” for more details on dead-band delay operations.

The P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches. Alternatively, P1B can be assigned to PORTH<7> by programming the ECCPMX configuration bit to ‘0’. See Table 18-1, Table 18-2 and Table 18-3 for more information. The associated TRIS bit must be cleared to configure P1A and P1B as outputs.

FIGURE 18-4: HALF-BRIDGE PWM OUTPUT

Period

 

Period

Duty Cycle

P1A(2)

td

td P1B(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1)

 

(1)

 

(1)

 

 

 

 

 

 

 

 

 

 

 

 

td = Dead Band Delay

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signals are shown as active-high.

FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

Standard Half-Bridge Circuit (“Push-Pull”)

V+

 

PIC18F6X27/6X22/8X27/8X22

FET

 

 

Driver

+

 

 

P1A

 

V

 

 

-

 

FET

Load

 

 

 

Driver

+

 

 

P1B

 

V

 

 

-

 

 

V-

Half-Bridge Output Driving a Full-Bridge Circuit

 

V+

 

PIC18F6X27/6X22/8X27/8X22

 

 

FET

 

FET

Driver

 

Driver

P1A

 

 

FET

Load

FET

 

Driver

 

Driver

P1B

 

 

 

V-

 

DS39646B-page 196

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

18.4.5FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 18-6.

P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. Alternatively, P1B and P1C can be assigned to PORTH<7> and PORTH<6>, respectively, by programming the ECCPMX configuration bit to ‘0’. See Table 18-1, Table 18-2 and Table 18-3 for more information. The associated bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs.

FIGURE 18-6: FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

P1A(2)

Duty Cycle

P1B(2)

P1C(2)

P1D(2)

(1)

 

 

 

 

 

(1)

 

 

 

 

 

 

 

 

Reverse Mode

Period

Duty Cycle

P1A(2)

P1B(2)

P1C(2)

P1D(2)

(1)

 

 

 

(1)

 

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signal is shown as active-high.

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 197

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