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PIC18F8722 FAMILY

18.1ECCP Outputs and Configuration

Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCPx pin assignments are constant, while others change based on device configuration. For those pins that do change, the controlling bits are:

CCP2MX configuration bit (CONFIG3H<0>)

ECCPMX configuration bit (CONFIG3H<1>)

Program memory mode (set by configuration bits, CONFIG3L<1:0>)

The pin assignments for the Enhanced CCP modules are summarized in Table 18-1, Table 18-2 and Table 18-3. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for the corresponding port pins must also be set as outputs.

18.1.1USE OF CCP4 AND CCP5 WITH ECCP1 AND ECCP3

Only the ECCP2 module has four dedicated output pins available for use. Assuming that the I/O ports or other multiplexed functions on those pins are not needed, they may be used whenever needed without interfering with any other CCP module.

ECCP1 and ECCP3, on the other hand, only have three dedicated output pins: ECCPx/P3A, PxB and PxC. Whenever these modules are configured for Quad PWM mode, the pin used for CCP4 or CCP5 takes priority over the D output pins for ECCP3 and ECCP1, respectively.

18.1.2ECCP MODULE OUTPUTS, PROGRAM MEMORY MODES AND EMB ADDRESS BUS WIDTH

For PIC18F8527/8622/8627/8722 devices, the program memory mode of the device (Section 7.2 “Address and Data Width” and Section 7.4 “Program Memory Modes and the External Memory Bus”) impacts both pin multiplexing and the operation of the module.

The ECCP2 input/output (ECCP2/P2A) can be multiplexed to one of three pins. By default, this is RC1 for all devices; in this case, the default is in effect when CCP2MX is set and the device is operating in Microcontroller mode. With PIC18F8527/8622/8627/8722 devices, three other options exist. When CCP2MX is not set (= 0) and the device is in Microcontroller mode, ECCP2/P2A is multiplexed to RE7; in all other program memory modes, it is multiplexed to RB3.

Another option is for ECCPMX to be set while the device is operating in one of the three other program memory modes. In this case, ECCP1 and ECCP3 operate as compatible (i.e., single output) CCP modules. The pins used by their other outputs (PxB through PxD) are available for other multiplexed functions. ECCP2 continues to operate as an Enhanced CCP module regardless of the program memory mode.

The final option is that the ABW<1:0> configuration bits can be used to select 8, 12, 16 or 20-bit EMB addressing. Pins not assigned to EMB address pins are available for peripheral or port functions.

DS39646B-page 188

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1

ECCP Mode

CCP1CON

RC2

RE6

RE5

RG4

RH7

RH6

Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIC18F6527/6622/6627/6722 Devices:

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP1

RE6

RE5

RG4/CCP5

N/A

N/A

Dual PWM

 

10xx 11xx

P1A

P1B

RE5

RG4/CCP5

N/A

N/A

Quad PWM

x1xx 11xx

P1A

P1B

P1C

CCP5/P1D(1)

N/A

N/A

 

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, Microcontroller mode:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP1

RE6

RE5

RG4/CCP5

RH7/AN15

RH6/AN14

Dual PWM

 

10xx 11xx

P1A

P1B

RE5

RG4/CCP5

RH7/AN15

RH6/AN14

Quad PWM

x1xx 11xx

P1A

P1B

P1C

CCP5/P1D(1)

RH7/AN15

RH6/AN14

 

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, Microcontroller mode:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP1

RE6

RE5

RG4/CCP5

RH7/AN15

RH6/AN14

Dual PWM

 

10xx 11xx

P1A

RE6

RE5

RG4/CCP5

P1B

RH6/AN14

Quad PWM

x1xx 11xx

P1A

RE6

RE5

CCP5/P1D(1)

P1B

P1C

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, all other Program Memory modes:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP1

AD14(2)

AD13(2)

RG4/CCP5

RH7/AN15

RH6/AN14

Dual PWM

 

10xx 11xx

P1A

P1B/AD14(2)

AD13(2)

RG4/CCP5

RH7/AN15

RH6/AN14

Quad PWM

x1xx 11xx

P1A

P1B/AD14(2)

P1C/AD13(2)

CCP5/P1D(1)

RH7/AN15

RH6/AN14

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, all other Program Memory modes:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP1

AD14(2)

AD13(2)

RG4/CCP5

RH7/AN15

RH6/AN14

Dual PWM

 

10xx 11xx

P1A

AD14(2)

AD13(2)

RG4/CCP5

P1B

RH6/AN14

Quad PWM

x1xx 11xx

P1A

AD14(2)

AD13(2)

CCP5/P1D(1)

P1B

P1C

Legend:

x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.

Note 1:

With ECCP1 in Quad PWM mode, the CCP5 module’s output overrides P1D.

 

 

2:The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function.

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 189

PIC18F8722 FAMILY

TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2

ECCP Mode

CCP2CON

 

RB3

RC1

RE7

RE2

RE1

RE0

Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIC18F6527/6622/6627/6722 Devices, CCP2MX = 1:

 

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

 

RB3/INT3

ECCP2

RE7

RE2

RE1

RE0

Dual PWM

10xx 11xx

 

RB3/INT3

P2A

RE7

P2B

RE1

RE0

Quad PWM

x1xx 11xx

 

RB3/INT3

P2A

RE7

P2B

P2C

P2D

 

 

PIC18F6527/6622/6627/6722 Devices CCP2MX = 0:

 

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

 

RB3/INT3

RC1/T1OSI

ECCP2

RE2

RE1

RE0

Dual PWM

10xx 11xx

 

RB3/INT3

RC1/T1OSI

P2A

P2B

RE1

RE0

Quad PWM

x1xx 11xx

 

RB3/INT3

RC1/T1OSI

P2A

P2B

P2C

P2D

 

PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, Microcontroller mode:

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

 

RB3/INT3

ECCP2

RE7

RE2

RE1

RE0

Dual PWM

10xx 11xx

 

RB3/INT3

P2A

RE7

P2B

RE1

RE0

Quad PWM

x1xx 11xx

 

RB3/INT3

P2A

RE7

P2B

P2C

P2D

 

PIC18F8527/8622/8627/8722 Devices, CCP2MX = 0, Microcontroller mode:

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

 

RB3/INT3

RC1/T1OSI

ECCP2

RE2

RE1

RE0

Dual PWM

10xx 11xx

 

RB3/INT3

RC1/T1OSI

P2A

P2B

RE1

RE0

Quad PWM

x1xx 11xx

 

RB3/INT3

RC1/T1OSI

P2A

P2B

P2C

P2D

PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, all other Program Memory modes:

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

 

RB3/INT3

ECCP2

AD15(1)

AD10(1)

AD9(1)

AD8(1)

Dual PWM

10xx 11xx

 

RB3/INT3

P2A

AD15(1)

AD10/P2B(1)

AD9(1)

AD8(1)

Quad PWM

x1xx 11xx

 

RB3/INT3

P2A

AD15(1)

AD10/P2B(1)

AD9/P2C(1)

P2D/AD8(1)

PIC18F8527/8622/8627/8722 Devices, CCP2MX = 0, all other Program Memory modes:

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

 

ECCP2

RC1/T1OSI

AD15(1)

AD10(1)

AD9(1)

AD8(1)

Dual PWM

10xx 11xx

 

P2A

RC1/T1OSI

AD15(1)

AD10/P2B(1)

AD9(1)

AD8(1)

Quad PWM

x1xx 11xx

 

P2A

RC1/T1OSI

AD15(1)

AD10/P2B(1)

AD9/P2C(1)

P2D/AD8(1)

Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode.

Note 1: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function.

DS39646B-page 190

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3

ECCP Mode

CCP3CON

RG0

RE4

RE3

RG3

RH5

RH4

Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIC18F6527/6622/6627/6722 Devices:

 

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP3

RE4

RE3

RG3/CCP4

N/A

N/A

Dual PWM

 

10xx 11xx

P3A

P3B

RE3

RG3/CCP4

N/A

N/A

Quad PWM

x1xx 11xx

P3A

P3B

P3C

CCP4/P3D(1)

N/A

N/A

 

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, Microcontroller mode:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP3

RE4

RE3

RG3/CCP4

RH5/AN13

RH4/AN12

Dual PWM

 

10xx 11xx

P3A

P3B

RE3

RG3/CCP4

RH5/AN13

RH4/AN12

Quad PWM

x1xx 11xx

P3A

P3B

P3C

CCP4/P3D(1)

RH5/AN13

RH4/AN12

 

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, Microcontroller mode:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP3

RE4

RE3

RG3/CCP4

RH5/AN13

RH4/AN12

Dual PWM

 

10xx 11xx

P3A

RE4

RE3

RG3/CCP4

P3B

RH4/AN12

Quad PWM

x1xx 11xx

P3A

RE4

RE3

CCP4/P3D(1)

P3B

P3C

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, all other Program Memory modes:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP3

AD12(2)

AD10(2)

RG3/CCP4

RH5/AN13

RH4/AN12

Dual PWM

 

10xx 11xx

P3A

AD12/P3B(2)

AD10(2)

RG3/CCP4

RH5/AN13

RH4/AN12

Quad PWM

x1xx 11xx

P3A

AD12/P3B(2)

P3C/AD10(1)

CCP4/P3D(1)

RH5/AN13

RH4/AN12

 

PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, all other Program Memory modes:

 

 

 

 

 

 

 

 

 

Compatible CCP

00xx 11xx

ECCP3

AD12(2)

AD10(2)

RG3/CCP4

RH5/AN13

RH4/AN12

Dual PWM

 

10xx 11xx

P3A

AD12(2)

AD10(2)

RG3/CCP4

P3B

RH4/AN12

Quad PWM

x1xx 11xx

P3A

AD12(2)

AD10(2)

CCP4/P3D(1)

P3B

P3C

Legend:

x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode.

Note 1:

With ECCP3 in Quad PWM mode, the CCP4 module’s output overrides P3D.

 

 

2:The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function.

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 191

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