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PIC18F8722 FAMILY

The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation.

When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared.

The maximum PWM resolution (bits) for a given PWM frequency is given by the equation:

EQUATION 17-3:

FOSC log ---------------

FPWM

PWM Resolution (max) = -----------------------------bits

log(2)

Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared.

17.4.3SETUP FOR PWM OPERATION

The following steps should be taken when configuring the CCP module for PWM operation:

1.Set the PWM period by writing to the PR2 (PR4) register.

2.Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits.

3.Make the CCPx pin an output by clearing the appropriate TRIS bit.

4.Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON (T4CON).

5.Configure the CCPx module for PWM operation.

TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz

156.25 kHz

312.50 kHz

416.67 kHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer Prescaler (1, 4, 16)

16

4

1

1

1

1

 

 

 

 

 

 

 

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

 

 

 

 

 

 

 

Maximum Resolution (bits)

10

10

10

8

7

6.58

 

 

 

 

 

 

 

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 185

PIC18F8722 FAMILY

TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

on page

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

57

RCON

IPEN

SBOREN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

 

RI

TO

PD

POR

BOR

PIR1

PSPIF

ADIF

RC1IF

TX1IF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

60

PIE1

PSPIE

ADIE

RC1IE

TX1IE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

60

IPR1

PSPIP

ADIP

RC1IP

TX1IP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

60

PIR3

SSP2IF

BCL2IF

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

60

PIE3

SSP2IE

BCL2IF

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE

60

IPR3

SSP2IP

BCL2IP

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP

60

TMR2

Timer2 Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PR2

Timer2 Period Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

 

 

 

 

 

 

 

 

 

 

T2CON

T2OUTPS3

T2OUTPS2

T2OUTPS1

T2OUTPS0

TMR2ON

T2CKPS1

T2CKPS0

58

TMR4

Timer4 Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PR4

Timer4 Period Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

 

 

 

 

 

 

 

 

 

 

T4CON

T4OUTPS3

T4OUTPS2

T4OUTPS1

T4OUTPS0

TMR4ON

T4CKPS1

T4CKPS0

61

CCPR1L

Enhanced Capture/Compare/PWM Register 1 Low Byte

 

 

 

 

 

 

 

 

 

59

 

 

 

 

 

 

 

 

 

 

 

 

CCPR1H

Enhanced Capture/Compare/PWM Register 1 High Byte

 

 

 

 

 

 

 

 

 

59

 

 

 

 

 

 

 

 

 

 

 

 

CCPR2L

Enhanced Capture/Compare/PWM Register 2 Low Byte

 

 

 

 

 

 

 

 

 

59

 

 

 

 

 

 

 

 

 

 

 

 

CCPR2H

Enhanced Capture/Compare/PWM Register 2 High Byte

 

 

 

 

 

 

 

 

 

59

 

 

 

 

 

 

 

 

 

 

CCP4CON

DC4B1

DC4B0

CCP4M3

CCP4M2

CCP4M1

CCP4M0

61

CCP5CON

DC5B1

DC5B0

CCP5M3

CCP5M2

CCP5M1

CCP5M0

61

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4.

DS39646B-page 186

Preliminary

2004 Microchip Technology Inc.

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