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PIC18F8722 FAMILY

11.6PORTF, LATF and TRISF Registers

PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin).

The Data Latch register (LATF) is also memory mapped. Read-modify-write operations on the LATF register read and write the latched output value for PORTF.

All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.

PORTF is multiplexed with several analog peripheral functions, including the A/D converter and comparator inputs, as well as the comparator outputs. Pins RF1 through RF2 may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RF0:RF6 as digital inputs, it is necessary to turn off the A/D inputs.

Note 1: On a Power-on Reset, the RF6:RF0 pins are configured as analog inputs and read as ‘0’.

2:To configure PORTF as digital I/O, set the ADCON1 register.

EXAMPLE 11-6: INITIALIZING PORTF

CLRF

PORTF

; Initialize

PORTF by

 

 

; clearing output

 

 

; data latches

CLRF

LATF

; Alternate method

 

 

; to clear output

 

 

; data latches

MOVLW

0x0F

;

 

MOVWF

ADCON1

; Set PORTF as digital I/O

MOVLW

0xCF

; Value used

to

 

 

; initialize

data

 

 

; direction

 

MOVWF

TRISF

; Set RF3:RF0 as inputs

 

 

; RF5:RF4 as

outputs

 

 

; RF7:RF6 as

inputs

 

 

 

 

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 149

PIC18F8722 FAMILY

TABLE 11-11: PORTF FUNCTIONS

Pin Name

Function

TRIS

I/O

I/O

Description

Setting

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RF0/AN5

 

RF0

0

O

DIG

LATF<0> data output; not affected by analog input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<0> data input; disabled when analog input enabled.

 

 

 

 

 

 

 

 

 

 

 

AN5

1

I

ANA

A/D input channel 5. Default configuration on POR.

 

 

 

 

 

 

 

RF1/AN6/C2OUT

 

RF1

0

O

DIG

LATF<1> data output; not affected by analog input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<1> data input; disabled when analog input enabled.

 

 

 

 

 

 

 

 

 

 

 

AN6

1

I

ANA

A/D input channel 6. Default configuration on POR.

 

 

 

 

 

 

 

 

 

 

 

C2OUT

0

O

DIG

Comparator 2 output; takes priority over port data.

 

 

 

 

 

 

 

RF2/AN7/C1OUT

 

RF2

0

O

DIG

LATF<2> data output; not affected by analog input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<2> data input; disabled when analog input enabled.

 

 

 

 

 

 

 

 

 

 

 

AN7

1

I

ANA

A/D input channel 7. Default configuration on POR.

 

 

 

 

 

 

 

 

 

 

 

C1OUT

0

O

TTL

Comparator 1 output; takes priority over port data.

 

 

 

 

 

 

 

RF3/AN8

 

RF3

0

O

DIG

LATF<3> data output; not affected by analog input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<3> data input; disabled when analog input enabled.

 

 

 

 

 

 

 

 

 

 

 

AN8

1

I

ANA

A/D input channel 8 and Comparator C2+ input. Default input

 

 

 

 

 

 

 

 

 

configuration on POR; not affected by analog output.

 

 

 

 

 

 

 

RF4/AN9

 

RF4

0

O

DIG

LATF<4> data output; not affected by analog input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<4> data input; disabled when analog input enabled.

 

 

 

 

 

 

 

 

 

 

 

AN9

1

I

ANA

A/D input channel 9 and Comparator C2input. Default input

 

 

 

 

 

 

 

 

 

configuration on POR; does not affect digital output.

 

 

 

 

 

 

 

RF5/AN10/CVREF

 

RF5

0

O

DIG

LATF<5> data output; not affected by analog input. Disabled when

 

 

 

 

 

 

 

 

 

CVREF output enabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<5> data input; disabled when analog input enabled. Disabled

 

 

 

 

 

 

 

 

 

when CVREF output enabled.

 

 

 

 

 

 

 

 

 

 

 

AN10

1

I

ANA

A/D input channel 10 and Comparator C1+ input. Default input

 

 

 

 

 

 

 

 

 

configuration on POR; not affected by analog output.

 

 

 

 

 

 

 

 

 

 

 

CVREF

x

O

ANA

Comparator voltage reference output. Enabling this feature disables

 

 

 

 

 

 

 

 

 

digital I/O.

 

 

 

 

 

 

 

RF6/AN11

 

RF6

0

O

DIG

LATF<6> data output; not affected by analog input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<6> data input; disabled when analog input enabled.

 

 

 

 

 

 

 

 

 

 

 

AN11

1

I

ANA

A/D input channel 11 and Comparator C1input. Default input

 

 

 

 

 

 

 

 

 

configuration on POR; does not affect digital output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RF7/SS1

 

 

RF7

0

O

DIG

LATF<7> data output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTF<7> data input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

TTL

Slave select input for SSP (MSSP1 module).

 

 

 

 

SS1

 

1

 

 

 

 

 

 

 

 

 

 

Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

 

 

 

 

 

 

 

 

 

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

 

 

 

 

 

 

 

 

 

on page

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRISF

TRISF7

TRISF6

TRISF5

TRISF4

TRISF3

TRISF2

TRISF1

TRISF0

60

 

 

 

 

 

 

 

 

 

 

PORTF

RF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0

60

 

 

 

 

 

 

 

 

 

 

LATF

LATF7

LATF6

LATF5

LATF4

LATF3

LATF2

LATF1

LATF0

60

 

 

 

 

 

 

 

 

 

 

ADCON1

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

59

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

59

 

 

 

 

 

 

 

 

 

 

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.

DS39646B-page 150

Preliminary

2004 Microchip Technology Inc.

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