Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
Скачиваний:
9
Добавлен:
21.12.2020
Размер:
8.16 Mб
Скачать

PIC18F8722 FAMILY

11.5PORTE, TRISE and LATE Registers

PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin).

The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE.

All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.

Note: On a Power-on Reset, these pins are configured as digital inputs.

When the device is operating in Microcontroller mode, pin RE7 can be configured as the alternate peripheral pin for the ECCP2 module. This is done by clearing the CCP2MX configuration bit.

In 80-pin devices, PORTE is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled (80-pin devices only), PORTE is the high-order byte of the multiplexed address/data bus (AD15:AD8). The TRISE bits are also overridden.

When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0/AD8/RD/P2D, RE1/AD9/WR/P2C and RE2/AD10/CS/P2B) are configured as digital control inputs for the port. The control functions are summarized in Table 11-9. The reconfiguration occurs automatically when the PSPMODE control bit (PSPCON<4>) is set. Users must still make certain the the corresponding TRISE bits are set to configure these pins as digital inputs.

EXAMPLE 11-5: INITIALIZING PORTE

CLRF

PORTE

; Initialize

PORTE by

 

 

; clearing output

 

 

; data latches

CLRF

LATE

; Alternate method

 

 

; to clear output

 

 

; data latches

MOVLW

03h

; Value used

to

 

 

; initialize

data

 

 

; direction

 

MOVWF

TRISE

; Set RE<1:0> as inputs

 

 

; RE<7:2> as

outputs

 

 

 

 

DS39646B-page 146

Preliminary

2004 Microchip Technology Inc.

 

 

 

 

 

 

 

 

 

 

 

 

PIC18F8722 FAMILY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TABLE 11-9:

PORTE FUNCTIONS

 

 

 

 

 

Pin Name

Function

TRIS

I/O

I/O

Description

 

 

Setting

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RE0/AD8/

RE0

0

O

DIG

LATE<0> data output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD/P2D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTE<0> data input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD8(2)

x

O

DIG

External memory interface, address/data bit 8 output. Takes priority

 

 

 

 

 

 

 

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 8 input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

TTL

Parallel Slave Port read enable control input.

 

 

 

 

RD

 

 

1

 

 

 

 

 

 

 

 

 

 

 

P2D

0

O

DIG

ECCP2 Enhanced PWM output, channel D. May be configured for

 

 

 

 

 

 

 

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

 

 

 

 

 

 

 

port data.

 

 

 

 

 

 

 

 

RE1/AD9/

RE1

0

O

DIG

LATE<1> data output.

 

WR/P2C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTE<1> data input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD9(2)

x

O

DIG

External memory interface, address/data bit 9 output. Takes priority

 

 

 

 

 

 

 

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 9 input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

TTL

Parallel Slave Port write enable control input.

 

 

 

 

WR

 

1

 

 

 

 

 

 

 

 

 

 

 

P2C

0

O

DIG

ECCP2 Enhanced PWM output, channel C. May be configured for

 

 

 

 

 

 

 

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

 

 

 

 

 

 

 

port data.

 

 

 

 

 

 

 

 

RE2/AD10/

RE2

0

O

DIG

LATE<2> data output.

 

CS/P2B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTE<2> data input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD10(2)

x

O

DIG

External memory interface, address/data bit 10 output. Takes priority

 

 

 

 

 

 

 

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 10 input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

TTL

Parallel Slave Port chip select control input.

 

 

 

 

 

CS

 

1

 

 

 

 

 

 

 

 

 

 

 

P2B

0

O

DIG

ECCP2 Enhanced PWM output, channel B. May be configured for

 

 

 

 

 

 

 

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

 

 

 

 

 

 

 

port data.

 

 

 

 

 

 

 

 

RE3/AD11/P3C

RE3

0

O

DIG

LATE<3> data output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTE<3> data input.

 

 

 

 

 

 

 

 

 

 

 

AD11(2)

x

O

DIG

External memory interface, address/data bit 11 output. Takes priority

 

 

 

 

 

 

 

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 11 input.

 

 

 

 

 

 

 

 

 

 

 

P3C

0

O

DIG

ECCP3 Enhanced PWM output, channel C. May be configured for

 

 

 

 

 

 

 

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

 

 

 

 

 

 

 

port data.

 

 

 

 

 

 

 

 

RE4/AD12/P3B

RE4

0

O

DIG

LATE<4> data output.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

I

ST

PORTE<4> data input.

 

 

 

 

 

 

 

 

 

 

 

AD12(2)

x

O

DIG

External memory interface, address/data bit 12 output. Takes priority

 

 

 

 

 

 

 

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 12 input.

 

 

 

 

 

 

 

 

 

 

 

P3B

0

O

DIG

ECCP3 Enhanced PWM output, channel B. May be configured for

 

 

 

 

 

 

 

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

 

 

 

 

 

 

 

port data.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Legend:

PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

 

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1:

Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).

2:Implemented on 80-pin devices only.

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 147

PIC18F8722 FAMILY

TABLE 11-9:

PORTE FUNCTIONS (CONTINUED)

Pin Name

Function

TRIS

I/O

I/O

Description

Setting

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RE5/AD13/P1C

RE5

0

O

DIG

LATE<5> data output.

 

 

 

 

 

 

 

 

1

I

ST

PORTE<5> data input.

 

 

 

 

 

 

 

AD13(2)

x

O

DIG

External memory interface, address/data bit 13 output. Takes priority

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 13 input.

 

 

 

 

 

 

 

P1C

0

O

DIG

ECCP1 Enhanced PWM output, channel C. May be configured for

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

port data.

 

 

 

 

 

 

RE6/AD14/P1B

RE6

0

O

DIG

LATE<6> data output.

 

 

 

 

 

 

 

 

1

I

ST

PORTE<6> data input.

 

 

 

 

 

 

 

AD14(2)

x

O

DIG

External memory interface, address/data bit 14 output. Takes priority

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 14 input.

 

 

 

 

 

 

 

P1B

0

O

DIG

ECCP1 Enhanced PWM output, channel B. May be configured for

 

 

 

 

 

tri-state during Enhanced PWM shutdown events. Takes priority over

 

 

 

 

 

port data.

 

 

 

 

 

 

RE7/AD15/

RE7

0

O

DIG

LATE<7> data output.

ECCP2/P2A

 

 

 

 

 

 

1

I

ST

PORTE<7> data input.

 

 

 

 

 

 

 

 

 

AD15(2)

x

O

DIG

External memory interface, address/data bit 15 output. Takes priority

 

 

 

 

 

over ECCP and port data.

 

 

 

 

 

 

 

 

x

I

TTL

External memory interface, data bit 15 input.

 

 

 

 

 

 

 

ECCP2(1)

0

O

DIG

ECCP2 compare output and ECCP2 PWM output. Takes priority over

 

 

 

 

 

port data.

 

 

 

 

 

 

 

 

1

I

ST

ECCP2 capture input.

 

 

 

 

 

 

 

P2A(1)

0

O

DIG

ECCP2 Enhanced PWM output, channel A. Takes priority over port and

 

 

 

 

 

data. May be configured for tri-state during Enhanced PWM shutdown

 

 

 

 

 

events.

 

 

 

 

 

 

Legend:

PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

 

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1:

Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).

2:Implemented on 80-pin devices only.

TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

 

 

 

 

 

 

 

 

 

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

 

 

 

 

 

 

 

 

 

on page

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORTE

RE7

RE6

RE5

RE4

RE3

RE2

RE1

RE0

60

 

 

 

 

 

 

 

 

 

 

LATE

LATE7

LATE6

LATE5

LATE4

LATE3

LATE2

LATE1

LATE0

60

 

 

 

 

 

 

 

 

 

 

TRISE

TRISE7

TRISE6

TRISE5

TRISE4

TRISE3

TRISE2

TRISE1

TRISE0

60

 

 

 

 

 

 

 

 

 

 

DS39646B-page 148

Preliminary

2004 Microchip Technology Inc.

Соседние файлы в папке Склад