PIC18F8722 FAMILY
4.6Reset State of Registers
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset.
Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
TABLE 4-3: |
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION |
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FOR RCON REGISTER |
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Condition |
Program |
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RCON Register |
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STKPTR Register |
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Counter |
SBOREN |
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RI |
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TO |
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PD |
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POR |
BOR |
STKFUL |
STKUNF |
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Power-on Reset |
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0000h |
1 |
1 |
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1 |
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1 |
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0 |
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0 |
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0 |
0 |
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RESET Instruction |
0000h |
u(2) |
0 |
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u |
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u |
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u |
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u |
u |
u |
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Brown-out Reset |
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0000h |
u(2) |
1 |
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1 |
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1 |
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u |
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0 |
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u |
u |
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during Power-Managed |
0000h |
u(2) |
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MCLR |
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u |
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1 |
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u |
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u |
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u |
u |
u |
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Run Modes |
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during Power-Managed |
0000h |
u(2) |
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MCLR |
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u |
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1 |
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0 |
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u |
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u |
u |
u |
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Idle Modes and Sleep Mode |
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WDT Time-out during Full Power |
0000h |
u(2) |
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u |
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0 |
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u |
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u |
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u |
u |
u |
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or Power-Managed Run Mode |
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during Full Power |
0000h |
u(2) |
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MCLR |
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u |
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u |
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u |
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u |
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u |
u |
u |
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Execution |
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Stack Full Reset (STVREN = 1) |
0000h |
u(2) |
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u |
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u |
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u |
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u |
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u |
1 |
u |
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Stack Underflow Reset |
0000h |
u(2) |
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u |
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u |
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u |
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u |
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u |
u |
1 |
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(STVREN = 1) |
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Stack Underflow Error (not an |
0000h |
u(2) |
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u |
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u |
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u |
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u |
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u |
u |
1 |
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actual Reset, STVREN = 0) |
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WDT Time-out during |
PC + 2 |
u(2) |
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u |
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0 |
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0 |
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u |
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u |
u |
u |
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Power-Managed Idle or |
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Sleep Modes |
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Interrupt Exit from |
PC + 2(1) |
u(2) |
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u |
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u |
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0 |
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u |
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u |
u |
u |
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Power-Managed Modes |
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Legend: u = unchanged |
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Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h).
2:Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’.
DS39646B-page 56 |
Preliminary |
2004 Microchip Technology Inc. |
PIC18F8722 FAMILY
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS |
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MCLR Resets, |
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Register |
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Applicable Devices |
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Power-on Reset, |
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WDT Reset, |
Wake-up via WDT |
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Brown-out Reset |
RESET Instruction, |
or Interrupt |
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Stack Resets |
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TOSU |
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6X27 |
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6X22 |
8X27 |
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8X22 |
---0 0000 |
---0 0000 |
---0 uuuu(3) |
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TOSH |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu(3) |
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TOSL |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu(3) |
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STKPTR |
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6X27 |
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6X22 |
8X27 |
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8X22 |
00-0 0000 |
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uu-u uuuu |
uu-u uuuu(3) |
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PCLATU |
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6X27 |
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6X22 |
8X27 |
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8X22 |
---0 0000 |
---0 0000 |
---u uuuu |
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PCLATH |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu |
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PCL |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
PC + 2(2) |
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TBLPTRU |
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6X27 |
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6X22 |
8X27 |
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8X22 |
--00 0000 |
--00 0000 |
--uu uuuu |
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TBLPTRH |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu |
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TBLPTRL |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu |
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TABLAT |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
0000 |
0000 |
0000 |
uuuu uuuu |
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PRODH |
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6X27 |
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6X22 |
8X27 |
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8X22 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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PRODL |
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6X27 |
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6X22 |
8X27 |
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8X22 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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INTCON |
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6X27 |
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6X22 |
8X27 |
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8X22 |
0000 |
000x |
0000 |
000u |
uuuu uuuu(1) |
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INTCON2 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
1111 |
1111 |
1111 |
1111 |
uuuu uuuu(1) |
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INTCON3 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
1100 |
0000 |
1100 |
0000 |
uuuu uuuu(1) |
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INDF0 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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POSTINC0 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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POSTDEC0 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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PREINC0 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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PLUSW0 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
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FSR0H |
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6X27 |
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6X22 |
8X27 |
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8X22 |
---- 0000 |
---- 0000 |
---- uuuu |
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FSR0L |
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6X27 |
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6X22 |
8X27 |
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8X22 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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WREG |
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6X27 |
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6X22 |
8X27 |
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8X22 |
xxxx xxxx |
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uuuu uuuu |
uuuu uuuu |
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INDF1 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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POSTINC1 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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POSTDEC1 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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PREINC1 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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PLUSW1 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
N/A |
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Legend: |
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. |
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Shaded cells indicate conditions do not apply for the designated device. |
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Note 1: |
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). |
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2:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4:See Table 4-3 for Reset value for specific condition.
5:Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
2004 Microchip Technology Inc.
Preliminary
DS39646B-page 57
PIC18F8722 FAMILY
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
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MCLR Resets, |
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Register |
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Applicable Devices |
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Power-on Reset, |
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WDT Reset, |
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Wake-up via WDT |
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Brown-out Reset |
RESET Instruction, |
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or Interrupt |
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Stack Resets |
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FSR1H |
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6X27 |
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6X22 |
8X27 |
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8X22 |
---- 0000 |
---- 0000 |
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---- uuuu |
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FSR1L |
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6X27 |
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6X22 |
8X27 |
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8X22 |
xxxx xxxx |
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uuuu uuuu |
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uuuu uuuu |
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BSR |
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6X27 |
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6X22 |
8X27 |
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8X22 |
---- 0000 |
---- 0000 |
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---- uuuu |
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INDF2 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
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N/A |
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POSTINC2 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
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N/A |
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POSTDEC2 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
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N/A |
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PREINC2 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
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N/A |
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PLUSW2 |
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6X27 |
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6X22 |
8X27 |
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8X22 |
N/A |
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N/A |
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N/A |
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FSR2H |
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6X27 |
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6X22 |
8X27 |
|
8X22 |
---- 0000 |
---- 0000 |
|
---- uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
FSR2L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
STATUS |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
---x xxxx |
|
---u uuuu |
|
---u uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
TMR0H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
TMR0L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
T0CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
OSCCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0100 |
q000 |
0100 |
q000 |
|
uuuu uuqu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
HLVDCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0-00 0101 |
0-00 0101 |
|
u-uu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
WDTCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
---- ---0 |
---- ---0 |
|
---- ---u |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
RCON(4) |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0q-1 11q0 |
|
0q-q qquu |
|
uq-u qquu |
|||
TMR1H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
TMR1L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
T1CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
|
u0uu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
TMR2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
PR2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
T2CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
-000 0000 |
-000 0000 |
|
-uuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
SSP1BUF |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SSP1ADD |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SSP1STAT |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SSP1CON1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SSP1CON2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
||||||||
Legend: |
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. |
|||||||||||||||
|
Shaded cells indicate conditions do not apply for the designated device. |
|
|
|
||||||||||||
Note 1: |
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). |
|
||||||||||||||
2:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4:See Table 4-3 for Reset value for specific condition.
5:Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
DS39646B-page 58 |
Preliminary |
2004 Microchip Technology Inc. |
PIC18F8722 FAMILY
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
MCLR Resets, |
|
|
|
||
Register |
|
|
Applicable Devices |
|
Power-on Reset, |
|
WDT Reset, |
|
Wake-up via WDT |
||||||||
|
|
|
Brown-out Reset |
RESET Instruction, |
|
or Interrupt |
|||||||||||
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
Stack Resets |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ADRESH |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
ADRESL |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
ADCON0 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
--00 0000 |
--00 0000 |
|
--uu uuuu |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
ADCON1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
--00 0000 |
--00 0000 |
|
--uu uuuu |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
ADCON2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0-00 0000 |
0-00 0000 |
|
u-uu uuuu |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CCPR1H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CCPR1L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CCP1CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CCPR2H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CCPR2L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CCP2CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CCPR3H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CCPR3L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CCP3CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
ECCP1AS |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CVRCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CMCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0111 |
0000 |
0111 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
TMR3H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
TMR3L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
T3CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
|
uuuu uuuu |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
PSPCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
---- |
0000 |
---- |
|
uuuu ---- |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
SPBRG1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
RCREG1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
TXREG1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
TXSTA1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0010 |
0000 |
0010 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
RCSTA1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
000x |
0000 |
000x |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
EEADRH |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
---- --00 |
---- --00 |
|
---- --uu |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
EEADR |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
EEDATA |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
EECON2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
0000 |
0000 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
EECON1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xx-0 x000 |
|
uu-0 u000 |
|
uu-u uuuu |
||||
|
|
|
|
|
|
|
|
|
|
||||||||
Legend: |
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. |
|
|||||||||||||||
|
Shaded cells indicate conditions do not apply for the designated device. |
|
|
|
|
||||||||||||
Note 1: |
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). |
|
|
||||||||||||||
2:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4:See Table 4-3 for Reset value for specific condition.
5:Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
2004 Microchip Technology Inc.
Preliminary
DS39646B-page 59
PIC18F8722 FAMILY
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
MCLR Resets, |
|
|
|
Register |
|
|
Applicable Devices |
|
Power-on Reset, |
|
WDT Reset, |
|
Wake-up via WDT |
||||||
|
|
|
Brown-out Reset |
RESET Instruction, |
|
or Interrupt |
|||||||||
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
Stack Resets |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IPR3 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PIR3 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu(1) |
|
PIE3 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
IPR2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
11-1 1111 |
11-1 1111 |
|
uu-u uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
PIR2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
00-0 0000 |
00-0 0000 |
|
uu-u uuuu(1) |
|||
PIE2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
00-0 0000 |
00-0 0000 |
|
uu-u uuuu |
|||
|
|
|
|
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|
IPR1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
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|
PIR1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu(1) |
|
PIE1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
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||
MEMCON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0-00 --00 |
0-00 --00 |
|
u-uu --uu |
|||
OSCTUNE |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
00-0 0000 |
00-0 0000 |
|
uu-u uuuu |
|||
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|
TRISJ |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
TRISH |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
TRISG |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
---1 1111 |
---1 1111 |
|
---u uuuu |
|||
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|
TRISF |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
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TRISE |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
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TRISD |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
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|
TRISC |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
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TRISB |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
1111 |
1111 |
|
uuuu uuuu |
|
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|
TRISA(5) |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111(5) |
1111 |
1111(5) |
|
uuuu uuuu(5) |
|
LATJ |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
LATH |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
LATG |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
--xx xxxx |
|
--uu uuuu |
|
--uu uuuu |
||
|
|
|
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||
LATF |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
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|
|
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|
|
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||
LATE |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
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||
LATD |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
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|
|
|
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|
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||
LATC |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
LATB |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
LATA(5) |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx(5) |
|
uuuu uuuu(5) |
|
uuuu uuuu(5) |
||
PORTJ |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
PORTH |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
|
PORTG |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
--xx xxxx |
|
--uu uuuu |
|
--uu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PORTF |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
x000 |
0000 |
|
u000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
PORTE |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
PORTD |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
PORTC |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
PORTB |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|||||||
Legend: |
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. |
||||||||||||||
|
Shaded cells indicate conditions do not apply for the designated device. |
|
|
|
|||||||||||
Note 1: |
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). |
|
|||||||||||||
2:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4:See Table 4-3 for Reset value for specific condition.
5:Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
DS39646B-page 60 |
Preliminary |
2004 Microchip Technology Inc. |
PIC18F8722 FAMILY
TABLE 4-4: |
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) |
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
MCLR Resets, |
|
|
|
Register |
|
|
Applicable Devices |
|
Power-on Reset, |
|
WDT Reset, |
|
Wake-up via WDT |
||||||
|
|
|
Brown-out Reset |
RESET Instruction, |
|
or Interrupt |
|||||||||
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
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|
|
Stack Resets |
|
|
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|
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|
|
|
|
|
|
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||
|
|
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|
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|
|
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|
|
|
PORTA(5) |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xx0x 0000(5) |
|
uu0u 0000(5) |
|
uuuu uuuu(5) |
||
SPBRGH1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
BAUDCON1 |
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
01-0 0-00 |
01-0 0-00 |
|
uu-u u-uu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPBRGH2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
BAUDCON2 |
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
01-0 0-00 |
01-0 0-00 |
|
uu-u u-uu |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ECCP1DEL |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TMR4 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PR4 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
1111 |
1111 |
|
uuuu uuuu |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
T4CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
-000 0000 |
-000 0000 |
|
-uuu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
CCPR4H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
CCPR4L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CCP4CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
--00 0000 |
--00 0000 |
|
--uu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
CCPR5H |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
CCPR5L |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CCP5CON |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
--00 0000 |
--00 0000 |
|
--uu uuuu |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPBRG2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RCREG2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TXREG2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TXSTA2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0010 |
0000 |
0010 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RCSTA2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
000x |
0000 |
000x |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ECCP3AS |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ECCP3DEL |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ECCP2AS |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ECCP2DEL |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SSP2BUF |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
xxxx xxxx |
|
uuuu uuuu |
|
uuuu uuuu |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SSP2ADD |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SSP2STAT |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SSP2CON1 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SSP2CON2 |
|
|
6X27 |
|
6X22 |
8X27 |
|
8X22 |
0000 |
0000 |
0000 |
0000 |
|
uuuu uuuu |
|
|
|
|
|
|
|
|
|
|
|||||||
Legend: |
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. |
||||||||||||||
|
Shaded cells indicate conditions do not apply for the designated device. |
|
|
|
|||||||||||
Note 1: |
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). |
|
|||||||||||||
2:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h).
3:When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4:See Table 4-3 for Reset value for specific condition.
5:Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.
2004 Microchip Technology Inc.
Preliminary
DS39646B-page 61
PIC18F8722 FAMILY
NOTES:
DS39646B-page 62 |
Preliminary |
2004 Microchip Technology Inc. |