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PIC18F8722 FAMILY

4.0RESET

The PIC18F8722 family of devices differentiates between various kinds of Reset:

a)Power-on Reset (POR)

b)MCLR Reset during normal operation

c)MCLR Reset during power-managed modes

d)Watchdog Timer (WDT) Reset (during execution)

e)Programmable Brown-out Reset (BOR)

f)RESET Instruction

g)Stack Full Reset

h)Stack Underflow Reset

This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in

Section 5.1.3.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 25.2 “Watchdog Timer (WDT)”.

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1.

4.1RCON Register

Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 “Reset State of Registers”.

The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in

Section 10.0 “Interrupts”. BOR is covered in Section 4.4 “Brown-out Reset (BOR)”.

FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

 

 

 

 

 

Instruction

 

 

 

 

 

Stack

Stack Full/Underflow Reset

 

 

Pointer

 

 

 

 

 

 

External Reset

 

 

MCLR

 

MCLRE

 

 

 

 

 

 

 

( )_IDLE

 

 

 

 

Sleep

 

 

 

 

WDT

 

 

 

 

Time-out

 

 

 

 

VDD Rise

POR Pulse

 

 

Detect

 

 

 

 

VDD

 

 

 

 

 

Brown-out

 

 

 

Reset

 

 

S

 

 

 

BOREN

 

 

 

 

 

OST/PWRT

 

 

 

 

 

OST

1024 Cycles

 

Chip_Reset

 

 

10-bit Ripple Counter

 

OSC1

 

R

Q

 

 

 

 

 

31 s

PWRT

64 ms

 

 

 

 

 

INTRC(1)

 

11-bit Ripple Counter

 

 

 

 

 

 

 

Enable PWRT

 

 

 

 

 

Enable OST(2)

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2:See Table 4-2 for time-out situations.

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 49

PIC18F8722 FAMILY

REGISTER 4-1: RCON: RESET CONTROL REGISTER

R/W-0 R/W-1(1)

U-0

R/W-1

R-1

R-1

R/W-0(2)

R/W-0

IPEN

SBOREN

 

RI

 

 

TO

 

 

PD

 

 

POR

 

 

BOR

 

bit 7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 0

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1)

If BOREN1:BOREN0 = 01: 1 = BOR is enabled

0 = BOR is disabled

If BOREN1:BOREN0 = 00, 10 or 11:

Bit is disabled and read as ‘0’.

bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)

0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

bit 2 PD: Power-down Detection Flag bit

 

 

1

=

Set by power-up or by the CLRWDT instruction

 

 

 

 

0

=

Set by execution of the SLEEP instruction

 

 

 

 

 

 

Power-on Reset Status bit(2)

 

 

bit 1

POR:

 

 

 

 

1

= A Power-on Reset has not occurred (set by firmware only)

 

 

 

0

= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

 

 

 

 

 

 

 

 

bit 0

BOR: Brown-out Reset Status bit

 

 

 

 

1

= A Brown-out Reset has not occurred (set by firmware only)

 

 

 

0

= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

 

 

 

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

 

 

 

 

 

 

 

 

 

 

 

 

 

2: The actual Reset value of

POR

is determined by the type of device Reset. See the

 

 

 

 

 

 

notes following this register and Section 4.6 “Reset State of Registers” for

 

 

 

 

 

 

additional information.

 

 

 

 

 

 

 

 

 

 

 

 

Legend:

 

 

 

 

 

 

 

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

 

 

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected.

2:Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR).

DS39646B-page 50

Preliminary

2004 Microchip Technology Inc.

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