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PIC18F8722 FAMILY

28.4.3TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 28-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

Q4 Q1 Q2 Q3 Q4 Q1

OSC1

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

3

4

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKO

TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1A

FOSC

External CLKI Frequency(1)

DC

1

MHz

XT, RC Oscillator mode

 

 

 

DC

25

MHz

HS Oscillator mode

 

 

 

DC

31.25

kHz

LP Oscillator mode

 

 

 

DC

40

MHz

EC Oscillator mode

 

 

Oscillator Frequency(1)

DC

4

MHz

RC Oscillator mode

 

 

 

0.1

4

MHz

XT Oscillator mode

 

 

 

4

25

MHz

HS Oscillator mode

 

 

 

4

10

MHz

HS + PLL Oscillator mode

 

 

 

5

200

kHz

LP Oscillator mode

 

 

 

 

 

 

 

1

TOSC

External CLKI Period(1)

1000

ns

XT, RC Oscillator mode

 

 

 

40

ns

HS Oscillator mode

 

 

 

32

s

LP Oscillator mode

 

 

 

25

ns

EC Oscillator mode

 

 

Oscillator Period(1)

250

ns

RC Oscillator mode

 

 

 

250

1

s

XT Oscillator mode

 

 

 

40

250

ns

HS Oscillator mode

 

 

 

100

250

ns

HS + PLL Oscillator mode

 

 

 

5

s

LP Oscillator mode

 

 

 

 

 

 

 

2

TCY

Instruction Cycle Time(1)

100

ns

TCY = 4/FOSC, Industrial

 

 

 

160

ns

TCY = 4/FOSC, Extended

 

 

 

 

 

 

 

3

TOSL,

External Clock in (OSC1)

30

ns

XT Oscillator mode

 

TOSH

High or Low Time

2.5

s

LP Oscillator mode

 

 

 

10

ns

HS Oscillator mode

 

 

 

 

 

 

 

4

TOSR,

External Clock in (OSC1)

20

ns

XT Oscillator mode

 

TOSF

Rise or Fall Time

50

ns

LP Oscillator mode

 

 

 

 

 

 

7.5

ns

HS Oscillator mode

 

 

 

 

 

 

 

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

DS39646B-page 400

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

TABLE 28-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)

Param

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

No.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

F10

FOSC

Oscillator Frequency Range

4

10

MHz

HS mode only

F11

FSYS

On-Chip VCO System Frequency

16

40

MHz

HS mode only

 

 

 

 

 

 

 

 

F12

trc

PLL Start-up Time (Lock Time)

2

ms

 

F13

CLK

CLKO Stability (Jitter)

-2

+2

%

 

 

 

 

 

 

 

 

 

Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested.

TABLE 28-8: AC CHARACTERISTICS:INTERNAL RC ACCURACY PIC18F6X27/6X22/8X27/8X22 (INDUSTRIAL, EXTENDED) PIC18LF6X27/6X22/8X27/8X22 (INDUSTRIAL)

PIC18LF6X27/6X22/8X27/8X22

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C TA +85°C for industrial

 

 

 

 

 

 

 

 

 

PIC18F6X27/6X22/8X27/8X22

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C TA +85°C for industrial

(Industrial, Extended)

 

 

 

-40°C TA +125°C for extended

 

 

 

 

 

 

Param

 

Device

Min

Typ

Max

Units

 

Conditions

No.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)

 

 

PIC18LF6X27/6X22/8X27/8X22

-2

+/-1

2

%

+25°C

 

VDD = 2.7-3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

-5

5

%

-10°C to +85°C

 

VDD = 2.7-3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

-10

+/-1

10

%

-40°C to +85°C

 

VDD = 2.7-3.3V

 

 

 

 

 

 

 

 

 

 

 

 

PIC18F6X27/6X22/8X27/8X22

-2

+/-1

2

%

+25°C

 

VDD = 4.5-5.5V

 

 

 

-5

5

%

-10°C to +85°C

 

VDD = 4.5-5.5V

 

 

 

-10

+/-1

10

%

-40°C to +85°C

 

VDD = 4.5-5.5V

 

INTRC Accuracy @ Freq = 31 kHz(2)

 

 

 

 

 

 

 

 

PIC18LF6X27/6X22/8X27/8X22

-15

15

%

-40°C to +85°C

 

VDD = 2.7-3.3V

 

 

 

 

 

 

 

 

 

 

 

 

PIC18F6X27/6X22/8X27/8X22

-15

+/-8

15

%

-40°C to +85°C

 

VDD = 4.5-5.5V

Legend:

Shading of rows is to assist in readability of the table.

 

 

 

 

Note 1:

Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.

2:INTRC frequency after calibration.

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 401

PIC18F8722 FAMILY

FIGURE 28-7: CLKO AND I/O TIMING

 

Q4

Q1

 

Q2

Q3

OSC1

 

 

 

 

 

 

 

10

 

 

11

CLKO

 

 

 

 

 

 

 

13

19

18

12

 

 

14

16

 

 

 

 

 

I/O pin

 

 

 

 

 

(Input)

 

 

 

 

 

 

 

17

 

15

 

I/O pin

Old Value

 

 

New Value

 

(Output)

 

 

 

 

 

 

 

 

 

 

20, 21

 

 

 

Note:

Refer to Figure 28-5 for load conditions.

 

 

 

TABLE 28-9: CLKO AND I/O TIMING REQUIREMENTS

Param

 

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

No.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

TOSH2CKL

OSC1 ↑ to CLKO ↓

 

75

200

ns

(Note 1)

 

 

 

 

 

 

 

 

 

 

 

11

 

 

TOSH2CKH

OSC1 ↑ to CLKO ↑

 

75

200

ns

(Note 1)

12

 

 

TCKR

CLKO Rise Time

 

35

100

ns

(Note 1)

 

 

 

 

 

 

 

 

 

 

 

13

 

 

TCKF

CLKO Fall Time

 

35

100

ns

(Note 1)

 

 

 

 

 

 

 

 

 

 

 

14

 

 

TCKL2IOV

CLKO ↓ to Port Out Valid

 

0.5 TCY + 20

ns

(Note 1)

15

 

 

TIOV2CKH

Port In Valid before CLKO ↑

0.25 TCY + 25

ns

(Note 1)

 

 

 

 

 

 

 

 

 

 

 

16

 

 

TCKH2IOI

Port In Hold after CLKO ↑

 

0

ns

(Note 1)

 

 

 

 

 

 

 

 

 

 

17

 

 

TOSH2IOV

OSC1 ↑ (Q1 cycle) to Port Out Valid

50

150

ns

 

18

 

 

TOSH2IOI

OSC1 ↑ (Q2 cycle) to

 

PIC18FXXXX

100

ns

 

 

 

 

 

 

Port Input Invalid

 

 

 

 

 

 

 

18A

 

 

 

 

 

PIC18LFXXXX

200

ns

VDD = 2.0V

 

 

 

 

(I/O in hold time)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

 

TIOV2OSH

Port Input Valid to OSC1 ↑ (I/O in setup

0

ns

 

 

 

 

 

 

time)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

TIOR

Port Output Rise Time

 

PIC18FXXXX

10

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20A

 

 

 

 

 

 

PIC18LFXXXX

60

ns

VDD = 2.0V

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

TIOF

Port Output Fall Time

 

PIC18FXXXX

10

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21A

 

 

 

 

 

 

PIC18LFXXXX

60

ns

VDD = 2.0V

 

 

 

 

 

 

 

 

 

 

 

 

22†

 

 

TINP

INT pin High or Low Time

 

TCY

ns

 

 

 

 

 

 

 

 

 

 

 

23†

 

 

TRBP

RB7:RB4 Change INT High or Low Time

TCY

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

These parameters are asynchronous events not related to any internal clock edges.

 

 

Note

1:

Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

 

 

 

DS39646B-page 402

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

FIGURE 28-8: PROGRAM MEMORY READ TIMING DIAGRAM

Q1

Q2

Q3

Q4

Q1

Q2

OSC1

 

 

 

 

 

A<19:16>

 

Address

 

 

Address

BA0

 

 

 

 

 

 

 

 

AD<15:0>

Address

 

Data from External

 

Address

 

150

160

163

 

 

 

 

 

 

 

151

 

162

161

 

 

 

155

 

 

 

 

 

166

 

 

 

 

 

167

 

 

 

ALE

 

168

 

 

 

164

 

 

 

 

 

 

 

 

 

 

171

169

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

171A

 

 

 

 

OE

 

 

 

 

 

 

 

 

165

 

 

Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.

 

 

TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS

Param.

Symbol

 

 

 

 

 

 

 

Characteristics

Min

Typ

Max

Units

No

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

150

TadV2alL

 

Address Out Valid to ALE ↓ (address

0.25 TCY – 10

ns

 

 

 

setup time)

 

 

 

 

 

 

 

 

 

 

 

 

151

TalL2adl

 

ALE ↓ to Address Out Invalid (address

5

ns

 

 

 

hold time)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

155

TalL2oeL

ALE ↓ to

 

 

10

0.125 TCY

ns

OE

160

TadZ2oeL

 

AD high-Z to

 

↓ (bus release to

 

 

0

ns

OE

OE)

161

ToeH2adD

 

 

 

↑ to AD Driven

0.125 TCY – 5

ns

 

OE

162

TadV2oeH

LS Data Valid before

 

↑ (data setup time)

20

ns

OE

163

ToeH2adl

 

 

 

↑ to Data In Invalid (data hold time)

0

ns

 

OE

164

TalH2alL

ALE Pulse Width

TCY

ns

 

 

 

 

 

 

 

 

 

165

ToeL2oeH

 

 

 

Pulse Width

0.5 TCY – 5

0.5 TCY

ns

 

OE

 

 

 

 

 

 

 

 

166

TalH2alH

 

ALE ↑ to ALE ↑ (cycle time)

0.25 TCY

ns

167

Tacc

Address Valid to Data Valid

0.75 TCY – 25

ns

 

 

 

 

 

 

 

 

 

168

Toe

 

 

 

↓ to Data Valid

 

0.5 TCY – 25

ns

 

OE

 

169

TalL2oeH

 

ALE ↓ to

 

0.625 TCY – 10

0.625 TCY + 10

ns

 

OE

171

TalH2csL

Chip Enable Active to ALE ↓

0.25 TCY – 20

ns

 

 

 

 

 

 

 

 

171A

TubL2oeH

 

AD Valid to Chip Enable Active

10

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 403

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