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PIC18F8722 FAMILY

The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF- pins.

The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the converter, which generates the result via successive approximation.

A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted.

Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF (PIR1<6>), is set. The block diagram of the A/D module is shown in Figure 21-1.

FIGURE 21-1: A/D BLOCK DIAGRAM

CHS3:CHS0

1111 AN15(1)

1110 AN14(1)

1101

AN13(1)

1100 AN12(1)

1011

AN11

1010

AN10

 

 

 

1001

 

 

 

AN9

 

 

 

1000

 

 

 

AN8

 

 

 

0111

 

 

 

AN7

 

 

 

0110

 

 

 

AN6

 

 

 

0101

 

 

 

AN5

 

 

 

0100

 

 

VAIN

AN4

 

 

 

10-Bit

 

(Input Voltage)

0011

 

AN3

Converter

 

 

 

A/D

 

 

0010

 

 

 

AN2

 

 

VCFG1:VCFG0

0001

 

 

AN1

 

 

AVDD

0000

 

 

 

AN0

 

VREF+

X0

 

Reference

X1

 

 

1X

 

Voltage

VREF-

 

0X

 

 

 

 

 

 

 

 

 

AVSS

Note 1: Channels AN12 through AN15 are not available on 64-pin devices.

2:I/O pins have diode protection to VDD and VSS.

DS39646B-page 274

Preliminary

2004 Microchip Technology Inc.

PIC18F8722 FAMILY

The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset.

5.Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

OR

After the A/D module has been configured as desired,

 

 

• Waiting for the A/D interrupt

 

 

 

 

6.

 

Read A/D Result registers (ADRESH:ADRESL);

the

selected channel

must be acquired

before the

 

 

 

clear bit ADIF, if required.

 

 

 

 

conversion is started. The analog input channels must

 

 

 

 

 

 

7.

For next conversion, go to step 1 or step 2, as

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 21.1

 

 

required. The A/D conversion time per bit is

“A/D Acquisition Requirements”. After this acquisi-

 

 

defined as TAD. A minimum wait of 2 TAD is

tion time has elapsed, the A/D conversion can be

 

 

required before the next acquisition starts.

 

 

started. An acquisition time can be programmed to

 

 

 

 

 

 

 

 

 

 

 

 

occur between setting the GO/DONE bit and the actual

FIGURE 21-2:

 

A/D TRANSFER FUNCTION

start of the conversion.

 

 

 

 

 

 

 

 

 

 

 

 

 

The following steps should be followed to perform an A/D

 

 

3FFh

 

 

 

 

 

 

 

 

 

conversion:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.

Configure the A/D module:

 

 

Output

3FEh

 

 

 

 

 

 

 

 

 

 

Configure analog pins, voltage reference and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

digital I/O (ADCON1)

 

 

Code

 

 

 

 

 

 

 

 

 

 

 

Select A/D input channel (ADCON0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Digital

 

 

 

 

 

 

 

 

 

 

 

• Select A/D acquisition time (ADCON2)

 

003h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select A/D conversion clock (ADCON2)

 

 

002h

 

 

 

 

 

 

 

 

 

 

Turn on A/D module (ADCON0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.

Configure A/D interrupt (if desired):

 

 

 

001h

 

 

 

 

 

 

 

 

 

 

Clear ADIF bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set ADIE bit

 

 

 

 

000h

LSB

 

LSB

 

LSB

LSB

 

LSB

 

4.

Set GIE bit

 

 

 

 

LSB

LSB

LSB

LSB

LSB

Start conversion:

 

 

 

 

0.5

1

1.5

2

2.5

3

1022

1022.5

1023

1023.5

3.

Wait the required acquisition time (if required).

 

 

 

 

 

 

 

 

 

 

 

 

 

Set GO/DONE bit (ADCON0 register)

 

 

 

 

 

Analog Input Voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIGURE 21-3:

ANALOG INPUT MODEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

 

 

 

Sampling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 0.6V

 

 

 

Switch

 

 

 

 

 

 

 

 

 

 

ANx

 

 

 

SS

 

 

 

 

 

 

 

 

 

 

Rs

 

 

RIC ≤ 1k

RSS

 

 

 

 

 

 

 

 

VAIN

CPIN

 

ILEAKAGE

 

 

 

 

CHOLD = 25 pF

 

 

 

 

 

5 pF

VT = 0.6V

 

 

 

 

 

 

 

 

 

 

± 100 nA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

Legend: CPIN

= input capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

VT

= threshold voltage

 

6V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILEAKAGE

= leakage current at the pin due to

VDD

5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4V

 

 

 

 

 

 

 

 

 

 

 

 

various junctions

 

 

 

 

 

 

 

 

 

 

 

 

 

3V

 

 

 

 

 

 

 

 

 

 

 

RIC

= interconnect resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

2V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS

= sampling switch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CHOLD

= sample/hold capacitance (from DAC)

 

1 2 3 4

 

RSS

= sampling switch resistance

 

 

 

 

Sampling Switch (kΩ)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2004 Microchip Technology Inc.

Preliminary

DS39646B-page 275

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