Architectural Overview

1.4Functional Overview

The following sections provide an overview of the features of the LM3S6965 microcontroller. The pagenumberinparenthesisindicateswherethatfeatureisdiscussedindetail. Orderingandsupport information can be found in “Ordering and Contact Information” on page 614.

1.4.1ARM Cortex™-M3

1.4.1.1Processor Core (see page 43)

All members of the Stellaris® product family, including the LM3S6965 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

“ARM Cortex-M3 Processor Core” on page 43 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.

1.4.1.2System Timer (SysTick) (see page 46)

Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example:

■An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine.

■A high-speed alarm timer using the system clock.

■A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter.

■A simple counter. Software can use this to measure time to completion and time used.

■Aninternalclocksourcecontrolbasedonmissing/meetingdurations. TheCOUNTFLAGbit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop.

1.4.1.3Nested Vectored Interrupt Controller (NVIC) (see page 52)

The LM3S6965 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM®Cortex™-M3core.TheNVICandCortex-M3prioritizeandhandleallexceptions.Allexceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. Theprocessorsupportstail-chaining,whichenablesback-to-backinterruptstobeperformedwithout the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 38 interrupts.

“Interrupts”onpage52providesanoverviewoftheNVICcontrollerandtheinterruptmap. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.

1.4.2Motor Control Peripherals

Toenhancemotorcontrol,theLM3S6965controllerfeaturesPulseWidthModulation(PWM)outputs

and the Quadrature Encoder Interface (QEI).

Preliminary