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LM3S6965 Microcontroller

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0xFEC

WDTPeriphID3

RO

0x0000.0001

Watchdog Peripheral Identification 3

273

0xFF0

WDTPCellID0

RO

0x0000.000D

Watchdog PrimeCell Identification 0

274

0xFF4

WDTPCellID1

RO

0x0000.00F0

Watchdog PrimeCell Identification 1

275

0xFF8

WDTPCellID2

RO

0x0000.0005

Watchdog PrimeCell Identification 2

276

0xFFC

WDTPCellID3

RO

0x0000.00B1

Watchdog PrimeCell Identification 3

277

11.5Register Descriptions

The remainder of this section lists and describes the WDT registers, in numerical order by address offset.

November 16, 2008

257

Preliminary

Watchdog Timer

Register 1: Watchdog Load (WDTLOAD), offset 0x000

This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.

Watchdog Load (WDTLOAD)

Base 0x4000.0000

Offset 0x000

Type R/W, reset 0xFFFF.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

WDTLoad

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

WDTLoad

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:0

WDTLoad

R/W

0xFFFF.FFFF

Watchdog Load Value

258

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 2: Watchdog Value (WDTVALUE), offset 0x004

This register contains the current count value of the timer.

Watchdog Value (WDTVALUE)

Base 0x4000.0000

Offset 0x004

Type RO, reset 0xFFFF.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

WDTValue

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

WDTValue

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:0

WDTValue

RO

0xFFFF.FFFF

Watchdog Value

 

 

 

 

Current value of the 32-bit down counter.

November 16, 2008

259

Preliminary

Watchdog Timer

Register 3: Watchdog Control (WDTCTL), offset 0x008

This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out.

When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset.

Watchdog Control (WDTCTL)

Base 0x4000.0000

Offset 0x008

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

RESEN

INTEN

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

RESEN

R/W

0

Watchdog Reset Enable

 

 

 

 

The RESEN values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

Disabled.

1 Enable the Watchdog module reset output.

0

INTEN

R/W

0

Watchdog Interrupt Enable

The INTEN values are defined as follows:

Value Description

0 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset).

1 Interrupt event enabled. Once enabled, all writes are ignored.

260

November 16, 2008

Preliminary

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