Watchdog Timer

11 Watchdog Timer

A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way.

The Stellaris® Watchdog Timer module has the following features:

■32-bit down counter with a programmable load register

■Separate watchdog clock with an enable

■Programmable interrupt generation logic with interrupt masking

■Lock register protection from runaway software

■Reset generation logic with an enable/disable

■User-enabled stalling when the controller asserts the CPU Halt flag during debug

TheWatchdogTimercanbeconfiguredtogenerateaninterrupttothecontrolleronitsfirsttime-out, andtogeneratearesetsignalonitssecondtime-out. OncetheWatchdogTimerhasbeenconfigured, the lock register can be written to prevent the timer configuration from being inadvertently altered.

Preliminary

LM3S6965 Microcontroller

11.1Block Diagram

Figure 11-1. WDT Module Block Diagram

Identification Registers

WDTPCellID0 WDTPeriphID0 WDTPeriphID4

WDTPCellID1 WDTPeriphID1 WDTPeriphID5

WDTPCellID2 WDTPeriphID2 WDTPeriphID6

WDTPCellID3 WDTPeriphID3 WDTPeriphID7

11.2Functional Description

The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software.

If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its secondtime-out,the32-bitcounterisloadedwiththevalueinthe WDTLOAD register,andcounting resumes from that value.

If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting.

Preliminary

Watchdog Timer

Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register.

TheWatchdogmoduleinterruptandresetgenerationcanbeenabledordisabledasrequired. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state.

11.3Initialization and Configuration

To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence:

1.Load the WDTLOAD register with the desired timer load value.

2.IftheWatchdogisconfiguredtotriggersystemresets,setthe RESEN bitinthe WDTCTL register.

3.Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.

If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551.

11.4Register Map

Table 11-1 on page 256 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.

Table 11-1. Watchdog Timer Register Map

Preliminary