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General-Purpose Timers

Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030

Thisregisterisusedin32-bitReal-TimeClockmodeand16-bitPWMandInputEdgeCountmodes.

GPTM TimerA Match (GPTMTAMATCHR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x030

Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

TAMRH

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

1

1

0

1

0

1

1

1

1

0

1

1

1

1

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

TAMRL

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

31:16

TAMRH

R/W

0xFFFF

 

 

 

(32-bit mode)

 

 

 

0x0000

 

 

 

(16-bit mode)

Description

GPTM TimerA Match Register High

When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events.

In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR.

15:0

TAMRL

R/W

0xFFFF GPTM TimerA Match Register Low

When configured for 32-bit Real-Time Clock (RTC) mode via the

GPTMCFG register, this value is compared to the lower half of

GPTMTAR, to determine match events.

When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal.

When configured for Edge Count mode, this value along with GPTMTAILR,determineshowmanyedgeeventsarecounted. Thetotal number of edge events counted is equal to the value in GPTMTAILR minus this value.

246

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034

This register is used in 16-bit PWM and Input Edge Count modes.

GPTM TimerB Match (GPTMTBMATCHR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x034

Type R/W, reset 0x0000.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

TBMRL

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

TBMRL

R/W

0xFFFF

GPTM TimerB Match Register Low

 

 

 

 

When configured for PWM mode, this value along with GPTMTBILR,

 

 

 

 

determines the duty cycle of the output PWM signal.

When configured for Edge Count mode, this value along with GPTMTBILR,determineshowmanyedgeeventsarecounted. Thetotal number of edge events counted is equal to the value in GPTMTBILR minus this value.

November 16, 2008

247

Preliminary

General-Purpose Timers

Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038

This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode.

GPTM TimerA Prescale (GPTMTAPR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x038

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

TAPSR

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

TAPSR

R/W

0x00

GPTM TimerA Prescale

 

 

 

 

Theregisterloadsthisvalueonawrite. Areadreturnsthecurrentvalue

 

 

 

 

of the register.

Refer to Table 10-2 on page 222 for more details and an example.

248

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C

This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode.

GPTM TimerB Prescale (GPTMTBPR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x03C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

TBPSR

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

TBPSR

R/W

0x00

GPTM TimerB Prescale

 

 

 

 

Theregisterloadsthisvalueonawrite. Areadreturnsthecurrentvalue

 

 

 

 

of this register.

Refer to Table 10-2 on page 222 for more details and an example.

November 16, 2008

249

Preliminary

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