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General-Purpose Timers

Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024

This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.

GPTM Interrupt Clear (GPTMICR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x024

Type W1C, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

reserved

 

 

CBECINT CBMCINT TBTOCINT

 

reserved

 

RTCCINT CAECINT CAMCINT TATOCINT

Type

RO

RO

RO

RO

RO

W1C

W1C

W1C

RO

RO

RO

RO

W1C

W1C

W1C

W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:11

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

10

CBECINT

W1C

0

GPTM CaptureB Event Interrupt Clear

 

 

 

 

The CBECINT values are defined as follows:

 

 

 

 

Value Description

0 The interrupt is unaffected.

1 The interrupt is cleared.

9

CBMCINT

W1C

0

GPTM CaptureB Match Interrupt Clear

The CBMCINT values are defined as follows:

Value Description

0 The interrupt is unaffected.

1 The interrupt is cleared.

8

TBTOCINT

W1C

0

GPTM TimerB Time-Out Interrupt Clear

The TBTOCINT values are defined as follows:

Value

Description

0

The interrupt is unaffected.

1

The interrupt is cleared.

7:4

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

242

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

3

RTCCINT

W1C

0

GPTM RTC Interrupt Clear

 

 

 

 

The RTCCINT values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

The interrupt is unaffected.

 

 

 

 

1

The interrupt is cleared.

2

CAECINT

W1C

0

GPTM CaptureA Event Interrupt Clear

 

 

 

 

The CAECINT values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

The interrupt is unaffected.

 

 

 

 

1

The interrupt is cleared.

1

CAMCINT

W1C

0

GPTM CaptureA Match Raw Interrupt

 

 

 

 

This is the CaptureA match interrupt status after masking.

0

TATOCINT

W1C

0

GPTM TimerA Time-Out Raw Interrupt

 

 

 

 

The TATOCINT values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

The interrupt is unaffected.

 

 

 

 

1

The interrupt is cleared.

November 16, 2008

243

Preliminary

General-Purpose Timers

Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028

This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.

GPTM TimerA Interval Load (GPTMTAILR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x028

Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

TAILRH

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

1

1

0

1

0

1

1

1

1

0

1

1

1

1

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

TAILRL

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

31:16

TAILRH

R/W

0xFFFF

 

 

 

(32-bit mode)

 

 

 

0x0000

 

 

 

(16-bit mode)

Description

GPTM TimerA Interval Load Register High

Whenconfiguredfor32-bitmodeviathe GPTMCFG register,the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR.

In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR.

15:0

TAILRL

R/W

0xFFFF GPTM TimerA Interval Load Register Low

For both 16and 32-bit modes, writing this field loads the counter for

TimerA. A read returns the current value of GPTMTAILR.

244

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C

This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.

GPTM TimerB Interval Load (GPTMTBILR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x02C

Type R/W, reset 0x0000.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

TBILRL

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

TBILRL

R/W

0xFFFF

GPTM TimerB Interval Load Register

 

 

 

 

When the GPTM is not configured as a 32-bit timer, a write to this field

 

 

 

 

updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads

 

 

 

 

return the current value of GPTMTBILR.

November 16, 2008

245

Preliminary

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