General-Purpose Timers
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
Thisregisterallowssoftwaretoenable/disableGPTMcontroller-levelinterrupts. Writinga1enables the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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CBEIM |
CBMIM |
TBTOIM |
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reserved |
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RTCIM |
CAEIM |
CAMIM |
TATOIM |
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Type |
RO |
RO |
RO |
RO |
RO |
R/W |
R/W |
R/W |
RO |
RO |
RO |
RO |
R/W |
R/W |
R/W |
R/W |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
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31:11 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
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10 |
CBEIM |
R/W |
0 |
GPTM CaptureB Event Interrupt Mask |
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The CBEIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
9 |
CBMIM |
R/W |
0 |
GPTM CaptureB Match Interrupt Mask |
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The CBMIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
8 |
TBTOIM |
R/W |
0 |
GPTM TimerB Time-Out Interrupt Mask |
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The TBTOIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
7:4 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
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|
|
compatibility with future products, the value of a reserved bit should be |
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|
preserved across a read-modify-write operation. |
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238 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Bit/Field |
Name |
Type |
Reset |
Description |
|
3 |
RTCIM |
R/W |
0 |
GPTM RTC Interrupt Mask |
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The RTCIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
2 |
CAEIM |
R/W |
0 |
GPTM CaptureA Event Interrupt Mask |
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The CAEIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
1 |
CAMIM |
R/W |
0 |
GPTM CaptureA Match Interrupt Mask |
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The CAMIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
0 |
TATOIM |
R/W |
0 |
GPTM TimerA Time-Out Interrupt Mask |
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The TATOIM values are defined as follows: |
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Value |
Description |
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0 |
Interrupt is disabled. |
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1 |
Interrupt is enabled. |
November 16, 2008 |
239 |
Preliminary
General-Purpose Timers
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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CBERIS |
CBMRIS |
TBTORIS |
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reserved |
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RTCRIS |
CAERIS |
CAMRIS |
TATORIS |
|
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:11 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
10 |
CBERIS |
RO |
0 |
GPTM CaptureB Event Raw Interrupt |
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This is the CaptureB Event interrupt status prior to masking. |
9 |
CBMRIS |
RO |
0 |
GPTM CaptureB Match Raw Interrupt |
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This is the CaptureB Match interrupt status prior to masking. |
8 |
TBTORIS |
RO |
0 |
GPTM TimerB Time-Out Raw Interrupt |
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This is the TimerB time-out interrupt status prior to masking. |
7:4 |
reserved |
RO |
0x0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
3 |
RTCRIS |
RO |
0 |
GPTM RTC Raw Interrupt |
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This is the RTC Event interrupt status prior to masking. |
2 |
CAERIS |
RO |
0 |
GPTM CaptureA Event Raw Interrupt |
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This is the CaptureA Event interrupt status prior to masking. |
1 |
CAMRIS |
RO |
0 |
GPTM CaptureA Match Raw Interrupt |
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This is the CaptureA Match interrupt status prior to masking. |
0 |
TATORIS |
RO |
0 |
GPTM TimerA Time-Out Raw Interrupt |
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This the TimerA time-out interrupt status prior to masking. |
240 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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|
reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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CBEMIS |
CBMMIS |
TBTOMIS |
|
reserved |
|
RTCMIS |
CAEMIS |
CAMMIS |
TATOMIS |
|
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:11 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
10 |
CBEMIS |
RO |
0 |
GPTM CaptureB Event Masked Interrupt |
|
|
|
|
This is the CaptureB event interrupt status after masking. |
9 |
CBMMIS |
RO |
0 |
GPTM CaptureB Match Masked Interrupt |
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|
|
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This is the CaptureB match interrupt status after masking. |
8 |
TBTOMIS |
RO |
0 |
GPTM TimerB Time-Out Masked Interrupt |
|
|
|
|
This is the TimerB time-out interrupt status after masking. |
7:4 |
reserved |
RO |
0x0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
3 |
RTCMIS |
RO |
0 |
GPTM RTC Masked Interrupt |
|
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|
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This is the RTC event interrupt status after masking. |
2 |
CAEMIS |
RO |
0 |
GPTM CaptureA Event Masked Interrupt |
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|
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This is the CaptureA event interrupt status after masking. |
1 |
CAMMIS |
RO |
0 |
GPTM CaptureA Match Masked Interrupt |
|
|
|
|
This is the CaptureA match interrupt status after masking. |
0 |
TATOMIS |
RO |
0 |
GPTM TimerA Time-Out Masked Interrupt |
|
|
|
|
This is the TimerA time-out interrupt status after masking. |
November 16, 2008 |
241 |
Preliminary