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LM3S6965 Microcontroller

Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008

This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2.

GPTM TimerB Mode (GPTMTBMR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x008

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

TBAMS

TBCMR

 

TBMR

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

TBAMS

R/W

0

GPTM TimerB Alternate Mode Select

 

 

 

 

The TBAMS values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

Capture mode is enabled.

 

 

 

 

1

PWM mode is enabled.

Note: ToenablePWMmode,youmustalsocleartheTBCMR

bit and set the TBMR field to 0x2.

2

TBCMR

R/W

0

GPTM TimerB Capture Mode

The TBCMR values are defined as follows:

Value Description

0 Edge-Count mode

1 Edge-Time mode

November 16, 2008

233

Preliminary

General-Purpose Timers

Bit/Field

Name

Type

Reset

Description

1:0

TBMR

R/W

0x0

GPTM TimerB Mode

 

 

 

 

The TBMR values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0x0

Reserved

 

 

 

 

0x1

One-Shot Timer mode

 

 

 

 

0x2

Periodic Timer mode

 

 

 

 

0x3

Capture mode

The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register.

In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB.

In 32-bit timer configuration, this register’s contents are ignored and

GPTMTAMR is used.

234

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 4: GPTM Control (GPTMCTL), offset 0x00C

This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module.

GPTM Control (GPTMCTL)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x00C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

reserved

TBPWML

TBOTE

reserved

TBEVENT

TBSTALL

TBEN

reserved

TAPWML

TAOTE

RTCEN

TAEVENT

TASTALL

TAEN

Type

RO

R/W

R/W

RO

R/W

R/W

R/W

R/W

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:15

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

14

TBPWML

R/W

0

GPTM TimerB PWM Output Level

 

 

 

 

The TBPWML values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

Output is unaffected.

 

 

 

 

1

Output is inverted.

13

TBOTE

R/W

0

GPTM TimerB Output Trigger Enable

 

 

 

 

The TBOTE values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

The output TimerB ADC trigger is disabled.

 

 

 

 

1

The output TimerB ADC trigger is enabled.

 

 

 

 

Inaddition,theADCmustbeenabledandthetimerselectedasatrigger

 

 

 

 

source with the EMn bit in the ADCEMUX register (see page 293).

12

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

235

Preliminary

General-Purpose Timers

Bit/Field

Name

Type

Reset

Description

11:10

TBEVENT

R/W

0x0

GPTM TimerB Event Mode

 

 

 

 

The TBEVENT values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0x0

Positive edge

 

 

 

 

0x1

Negative edge

 

 

 

 

0x2

Reserved

 

 

 

 

0x3

Both edges

9

TBSTALL

R/W

0

GPTM TimerB Stall Enable

 

 

 

 

The TBSTALL values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

TimerB stalling is disabled.

 

 

 

 

1

TimerB stalling is enabled.

8

TBEN

R/W

0

GPTM TimerB Enable

 

 

 

 

The TBEN values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

TimerB is disabled.

 

 

 

 

1

TimerB is enabled and begins counting or the capture logic is

 

 

 

 

 

enabled based on the GPTMCFG register.

7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

TAPWML

R/W

0

GPTM TimerA PWM Output Level

 

 

 

 

The TAPWML values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

Output is unaffected.

 

 

 

 

1

Output is inverted.

5

TAOTE

R/W

0

GPTM TimerA Output Trigger Enable

 

 

 

 

The TAOTE values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

The output TimerA ADC trigger is disabled.

 

 

 

 

1

The output TimerA ADC trigger is enabled.

 

 

 

 

Inaddition,theADCmustbeenabledandthetimerselectedasatrigger

 

 

 

 

source with the EMn bit in the ADCEMUX register (see page 293).

236

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

4

RTCEN

R/W

0

GPTM RTC Enable

 

 

 

 

The RTCEN values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

RTC counting is disabled.

 

 

 

 

1

RTC counting is enabled.

3:2

TAEVENT

R/W

0x0

GPTM TimerA Event Mode

 

 

 

 

The TAEVENT values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0x0

Positive edge

 

 

 

 

0x1

Negative edge

 

 

 

 

0x2

Reserved

 

 

 

 

0x3

Both edges

1

TASTALL

R/W

0

GPTM TimerA Stall Enable

 

 

 

 

The TASTALL values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

TimerA stalling is disabled.

 

 

 

 

1

TimerA stalling is enabled.

0

TAEN

R/W

0

GPTM TimerA Enable

 

 

 

 

The TAEN values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

TimerA is disabled.

 

 

 

 

1

TimerA is enabled and begins counting or the capture logic is

 

 

 

 

 

enabled based on the GPTMCFG register.

November 16, 2008

237

Preliminary

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