LM3S6965 Microcontroller
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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TBAMS |
TBCMR |
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TBMR |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
R/W |
R/W |
R/W |
R/W |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
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31:4 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
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3 |
TBAMS |
R/W |
0 |
GPTM TimerB Alternate Mode Select |
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The TBAMS values are defined as follows: |
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Value |
Description |
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0 |
Capture mode is enabled. |
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1 |
PWM mode is enabled. |
Note: ToenablePWMmode,youmustalsocleartheTBCMR
bit and set the TBMR field to 0x2.
2 |
TBCMR |
R/W |
0 |
GPTM TimerB Capture Mode |
The TBCMR values are defined as follows:
Value Description
0 Edge-Count mode
1 Edge-Time mode
November 16, 2008 |
233 |
Preliminary
General-Purpose Timers
Bit/Field |
Name |
Type |
Reset |
Description |
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1:0 |
TBMR |
R/W |
0x0 |
GPTM TimerB Mode |
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The TBMR values are defined as follows: |
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Value |
Description |
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0x0 |
Reserved |
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0x1 |
One-Shot Timer mode |
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0x2 |
Periodic Timer mode |
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0x3 |
Capture mode |
The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
234 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
TBPWML |
TBOTE |
reserved |
TBEVENT |
TBSTALL |
TBEN |
reserved |
TAPWML |
TAOTE |
RTCEN |
TAEVENT |
TASTALL |
TAEN |
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Type |
RO |
R/W |
R/W |
RO |
R/W |
R/W |
R/W |
R/W |
RO |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
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31:15 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
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14 |
TBPWML |
R/W |
0 |
GPTM TimerB PWM Output Level |
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The TBPWML values are defined as follows: |
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Value |
Description |
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0 |
Output is unaffected. |
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1 |
Output is inverted. |
13 |
TBOTE |
R/W |
0 |
GPTM TimerB Output Trigger Enable |
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The TBOTE values are defined as follows: |
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Value |
Description |
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0 |
The output TimerB ADC trigger is disabled. |
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1 |
The output TimerB ADC trigger is enabled. |
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Inaddition,theADCmustbeenabledandthetimerselectedasatrigger |
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source with the EMn bit in the ADCEMUX register (see page 293). |
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12 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
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November 16, 2008 |
235 |
Preliminary
General-Purpose Timers
Bit/Field |
Name |
Type |
Reset |
Description |
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11:10 |
TBEVENT |
R/W |
0x0 |
GPTM TimerB Event Mode |
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The TBEVENT values are defined as follows: |
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Value |
Description |
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0x0 |
Positive edge |
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0x1 |
Negative edge |
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0x2 |
Reserved |
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0x3 |
Both edges |
9 |
TBSTALL |
R/W |
0 |
GPTM TimerB Stall Enable |
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The TBSTALL values are defined as follows: |
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Value |
Description |
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0 |
TimerB stalling is disabled. |
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1 |
TimerB stalling is enabled. |
8 |
TBEN |
R/W |
0 |
GPTM TimerB Enable |
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The TBEN values are defined as follows: |
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Value |
Description |
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0 |
TimerB is disabled. |
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1 |
TimerB is enabled and begins counting or the capture logic is |
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enabled based on the GPTMCFG register. |
7 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
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|
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
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6 |
TAPWML |
R/W |
0 |
GPTM TimerA PWM Output Level |
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The TAPWML values are defined as follows: |
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Value |
Description |
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0 |
Output is unaffected. |
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1 |
Output is inverted. |
5 |
TAOTE |
R/W |
0 |
GPTM TimerA Output Trigger Enable |
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The TAOTE values are defined as follows: |
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Value |
Description |
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0 |
The output TimerA ADC trigger is disabled. |
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1 |
The output TimerA ADC trigger is enabled. |
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Inaddition,theADCmustbeenabledandthetimerselectedasatrigger |
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source with the EMn bit in the ADCEMUX register (see page 293). |
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236 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Bit/Field |
Name |
Type |
Reset |
Description |
|
4 |
RTCEN |
R/W |
0 |
GPTM RTC Enable |
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The RTCEN values are defined as follows: |
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Value |
Description |
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0 |
RTC counting is disabled. |
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1 |
RTC counting is enabled. |
3:2 |
TAEVENT |
R/W |
0x0 |
GPTM TimerA Event Mode |
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The TAEVENT values are defined as follows: |
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Value |
Description |
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0x0 |
Positive edge |
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0x1 |
Negative edge |
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0x2 |
Reserved |
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0x3 |
Both edges |
1 |
TASTALL |
R/W |
0 |
GPTM TimerA Stall Enable |
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The TASTALL values are defined as follows: |
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Value |
Description |
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0 |
TimerA stalling is disabled. |
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1 |
TimerA stalling is enabled. |
0 |
TAEN |
R/W |
0 |
GPTM TimerA Enable |
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The TAEN values are defined as follows: |
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Value |
Description |
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0 |
TimerA is disabled. |
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1 |
TimerA is enabled and begins counting or the capture logic is |
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enabled based on the GPTMCFG register. |
November 16, 2008 |
237 |
Preliminary