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LM3S6965 Microcontroller

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x020

GPTMMIS

RO

0x0000.0000

GPTM Masked Interrupt Status

241

0x024

GPTMICR

W1C

0x0000.0000

GPTM Interrupt Clear

242

 

 

 

0x0000.FFFF

 

 

0x028

GPTMTAILR

R/W

(16-bit mode)

GPTM TimerA Interval Load

244

0xFFFF.FFFF

 

 

 

 

 

 

 

 

(32-bit mode)

 

 

0x02C

GPTMTBILR

R/W

0x0000.FFFF

GPTM TimerB Interval Load

245

 

 

 

0x0000.FFFF

 

 

0x030

GPTMTAMATCHR

R/W

(16-bit mode)

GPTM TimerA Match

246

0xFFFF.FFFF

 

 

 

 

 

 

 

 

(32-bit mode)

 

 

0x034

GPTMTBMATCHR

R/W

0x0000.FFFF

GPTM TimerB Match

247

0x038

GPTMTAPR

R/W

0x0000.0000

GPTM TimerA Prescale

248

0x03C

GPTMTBPR

R/W

0x0000.0000

GPTM TimerB Prescale

249

0x040

GPTMTAPMR

R/W

0x0000.0000

GPTM TimerA Prescale Match

250

0x044

GPTMTBPMR

R/W

0x0000.0000

GPTM TimerB Prescale Match

251

 

 

 

0x0000.FFFF

 

 

0x048

GPTMTAR

RO

(16-bit mode)

GPTM TimerA

252

0xFFFF.FFFF

 

 

 

 

 

 

 

 

(32-bit mode)

 

 

0x04C

GPTMTBR

RO

0x0000.FFFF

GPTM TimerB

253

10.5Register Descriptions

TheremainderofthissectionlistsanddescribestheGPTMregisters,innumericalorderbyaddress

offset.

November 16, 2008

229

Preliminary

General-Purpose Timers

Register 1: GPTM Configuration (GPTMCFG), offset 0x000

This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32or 16-bit mode.

GPTM Configuration (GPTMCFG)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x000

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

GPTMCFG

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:3

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

2:0

GPTMCFG

R/W

0x0

GPTM Configuration

 

 

 

 

The GPTMCFG values are defined as follows:

 

 

 

 

Value Description

0x0 32-bit timer configuration.

0x1 32-bit real-time clock (RTC) counter configuration.

0x2 Reserved

0x3 Reserved

0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of

GPTMTAMR and GPTMTBMR.

230

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004

This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2.

GPTM TimerA Mode (GPTMTAMR)

Timer0 base: 0x4003.0000

Timer1 base: 0x4003.1000

Timer2 base: 0x4003.2000

Timer3 base: 0x4003.3000

Offset 0x004

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

TAAMS

TACMR

 

TAMR

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

TAAMS

R/W

0

GPTM TimerA Alternate Mode Select

 

 

 

 

The TAAMS values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

Capture mode is enabled.

 

 

 

 

1

PWM mode is enabled.

Note: ToenablePWMmode,youmustalsocleartheTACMR

bit and set the TAMR field to 0x2.

2

TACMR

R/W

0

GPTM TimerA Capture Mode

The TACMR values are defined as follows:

Value Description

0 Edge-Count mode

1 Edge-Time mode

November 16, 2008

231

Preliminary

General-Purpose Timers

Bit/Field

Name

Type

Reset

Description

1:0

TAMR

R/W

0x0

GPTM TimerA Mode

 

 

 

 

The TAMR values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0x0

Reserved

 

 

 

 

0x1

One-Shot Timer mode

 

 

 

 

0x2

Periodic Timer mode

 

 

 

 

0x3

Capture mode

The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit).

In 16-bit timer configuration, TAMR controls the 16-bit timer modes for

TimerA.

In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored.

232

November 16, 2008

Preliminary

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