LM3S6965 Microcontroller

Figure 10-4. 16-Bit PWM Mode Example

10.3Initialization and Configuration

To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register.

This section shows module initialization and configuration examples for each of the supported timer modes.

10.3.132-Bit One-Shot/Periodic Timer Mode

The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:

1.Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes.

2.Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.

3.Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):

a.Write a value of 0x1 for One-Shot mode.

b.Write a value of 0x2 for Periodic mode.

4.Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).

5.Ifinterruptsarerequired,setthe TATOIM bitinthe GPTM Interrupt Mask Register (GPTMIMR).

6.Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.

Preliminary

General-Purpose Timers

7.Pollthe TATORIS bitintheGPTMRIS registerorwaitfortheinterrupttobegenerated(ifenabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR).

In One-Shot mode, the timer stops counting after step 7 on page 226. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out.

10.3.232-Bit Real-Time Clock (RTC) Mode

To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4 pins. To enable the RTC feature, follow these steps:

1.Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.

2.Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.

3.Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).

4.Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.

5.If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).

6.Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.

When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.

10.3.316-Bit One-Shot/Periodic Timer Mode

A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:

1.Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2.Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.

3.Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:

a.Write a value of 0x1 for One-Shot mode.

b.Write a value of 0x2 for Periodic mode.

4.If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR).

5.Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).

6.Ifinterruptsarerequired,setthe TnTOIM bitinthe GPTM Interrupt Mask Register (GPTMIMR).

7.Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting.

8.Pollthe TnTORIS bitintheGPTMRIS registerorwaitfortheinterrupttobegenerated(ifenabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR).

Preliminary

LM3S6965 Microcontroller

In One-Shot mode, the timer stops counting after step 8 on page 226. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out.

10.3.416-Bit Input Edge Count Mode

A timer is configured to Input Edge Count mode by the following sequence:

1.Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2.Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.

3.In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3.

4.Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register.

5.Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.

6.Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.

7.If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.

8.Setthe TnEN bitinthe GPTMCTL registertoenablethetimerandbeginwaitingforedgeevents.

9.Pollthe CnMRIS bitinthe GPTMRIS registerorwaitfortheinterrupttobegenerated(ifenabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register.

In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 227 through step 9 on page 227.

10.3.516-Bit Input Edge Timing Mode

A timer is configured to Input Edge Timing mode by the following sequence:

1.Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2.Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.

3.In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3.

4.Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register.

5.Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.

6.If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.

7.SettheTnEN bitintheGPTMControl(GPTMCTL) registertoenablethetimerandstartcounting.

8.Pollthe CnERIS bitinthe GPTMRIS registerorwaitfortheinterrupttobegenerated(ifenabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM

Preliminary