General-Purpose Timers

Figure 10-3 on page 224 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events.

Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR).

Figure 10-3. 16-Bit Input Edge Time Mode Example

Input Signal

10.2.3.4 16-Bit PWM Mode

Note: The prescaler is not available in 16-Bit PWM mode.

The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2.

When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR andcontinuescountinguntildisabledbysoftwareclearingtheTnEN bitintheGPTMCTL register. No interrupts or status bits are asserted in PWM mode.

The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register.

Figure10-4onpage225showshowtogenerateanoutputPWMwitha1-msperiodanda66%duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A.

Preliminary