General-Purpose Timers

10.2Functional Description

The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface.

SoftwareconfigurestheGPTMusingtheGPTMConfiguration(GPTMCFG) register(seepage230), the GPTM TimerA Mode (GPTMTAMR) register (see page 231), and the GPTM TimerB Mode (GPTMTBMR) register (see page 233). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes.

10.2.1GPTM Reset Conditions

After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register(seepage244)andthe GPTM TimerB Interval Load (GPTMTBILR) register (see page 245). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register(seepage248)andthe GPTM TimerB Prescale (GPTMTBPR) register(see page 249).

10.2.232-Bit Timer Operating Modes

ThissectiondescribesthethreeGPTM32-bittimermodes(One-Shot,Periodic,andRTC)andtheir configuration.

The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTCmode)tothe GPTMConfiguration(GPTMCFG) register. Inbothconfigurations,certainGPTM registers are concatenated to form pseudo 32-bit registers. These registers include:

■GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 244

■GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 245

■GPTM TimerA (GPTMTAR) register [15:0], see page 252

■GPTM TimerB (GPTMTBR) register [15:0], see page 253

In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:

GPTMTBILR[15:0]:GPTMTAILR[15:0]

Likewise, a read access to GPTMTAR returns the value:

GPTMTBR[15:0]:GPTMTAR[15:0]

10.2.2.1 32-Bit One-Shot/Periodic Timer Mode

In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determinedbythevaluewrittentothe TAMR fieldofthe GPTM TimerA Mode (GPTMTAMR) register (see page 231), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.

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LM3S6965 Microcontroller

When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 235), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting.

Inadditiontoreloadingthecountvalue,theGPTMgeneratesinterruptsandtriggerswhenitreaches the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 240), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register(seepage242). Ifthetime-outinterruptisenabledinthe GPTM Interrupt Mask (GPTIMR) register(seepage238),theGPTMalsosetsthe TATOMIS bitinthe GPTM Masked Interrupt Status (GPTMMIS) register (see page 241). The ADC trigger is enabled by setting the

TAOTE bit in GPTMCTL.

If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value.

If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted.

10.2.2.2 32-Bit Real-Time Clock Timer Mode

In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loadedwithavalueof0x0000.0001. Allsubsequentloadvaluesmustbewrittentothe GPTM TimerA Match (GPTMTAMATCHR) register (see page 246) by the controller.

The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The clocksignalisthendivideddowntoa1Hzrateandispassedalongtotheinputofthe32-bitcounter.

When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.

If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL.

10.2.316-Bit Timer Operating Modes

The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 230). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both.

10.2.3.1 16-Bit One-Shot/Periodic Timer Mode

In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register.TheoptionalprescalerisloadedintotheGPTMTimernPrescale(GPTMTnPR) register.

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General-Purpose Timers

When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR onthenextcycle. Ifconfiguredtobeaone-shottimer,thetimerstops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting.

In addition to reloading the count value, the timer generates interrupts and triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger is enabled by setting the TnOTE bit in the GPTMCTL register.

If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value.

If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted.

The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).

Table 10-2. 16-Bit Timer With Prescaler Configurations

Prescale #Clock (T c)aMax TimeUnits

a. Tc is the clock period.

10.2.3.216-Bit Input Edge Count Mode

Note: Forrising-edgedetection,theinputsignalmustbeHighforatleasttwosystemclockperiods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency.

Note: The prescaler is not available in 16-Bit Input Edge Count mode.

In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted.

When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled foreventcapture. Eachinputeventonthe CCP pindecrementsthecounterby1untiltheeventcount matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).

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LM3S6965 Microcontroller

The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automaticallyclearsthe TnEN bitinthe GPTMCTL register. Oncetheeventcounthasbeenreached, all further events are ignored until TnEN is re-enabled by software.

Figure10-2onpage223showshowinputedgecountmodeworks. Inthiscase,thetimerstartvalue is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal.

Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register.

Figure 10-2. 16-Bit Input Edge Count Mode Example

Input Signal

10.2.3.3 16-Bit Input Edge Time Mode

Note: Forrising-edgedetection,theinputsignalmustbeHighforatleasttwosystemclockperiods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency.

Note: The prescaler is not available in 16-Bit Input Edge Time mode.

In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register.

When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. Whentheselectedinputeventisdetected,thecurrentTncountervalueiscapturedinthe GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked).

After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register.

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