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General-Purpose Input/Outputs (GPIOs)

9.1.6Identification

The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers.

9.2Initialization and Configuration

To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register.

On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 180 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-2 on page 181 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port.

Table 9-1. GPIO Pad Configuration Examples

Configuration

GPIO Register Bit Valuea

 

 

 

 

 

 

 

 

AFSEL DIR

 

ODR

DEN

PUR

PDR

DR2R

DR4R

DR8R

SLR

Digital Input (GPIO)

0

0

0

1

?

?

X

X

X

X

Digital Output (GPIO)

0

1

0

1

?

?

?

?

?

?

Open Drain Input

0

0

1

1

X

X

X

X

X

X

(GPIO)

 

 

 

 

 

 

 

 

 

 

Open Drain Output

0

1

1

1

X

X

?

?

?

?

(GPIO)

 

 

 

 

 

 

 

 

 

 

Open Drain

1

X

1

1

X

X

?

?

?

?

Input/Output (I2C)

 

 

 

 

 

 

 

 

 

 

Digital Input (Timer

1

X

0

1

?

?

X

X

X

X

CCP)

 

 

 

 

 

 

 

 

 

 

Digital Input (QEI)

1

X

0

1

?

?

X

X

X

X

Digital Output (PWM)

1

X

0

1

?

?

?

?

?

?

Digital Output (Timer

1

X

0

1

?

?

?

?

?

?

PWM)

 

 

 

 

 

 

 

 

 

 

Digital Input/Output

1

X

0

1

?

?

?

?

?

?

(SSI)

 

 

 

 

 

 

 

 

 

 

Digital Input/Output

1

X

0

1

?

?

?

?

?

?

(UART)

 

 

 

 

 

 

 

 

 

 

Analog Input

0

0

0

0

0

0

X

X

X

X

(Comparator)

 

 

 

 

 

 

 

 

 

 

Digital Output

1

X

0

1

?

?

?

?

?

?

(Comparator)

 

 

 

 

 

 

 

 

 

 

a. X=Ignored (don’t care bit)

?=Can be either 0 or 1, depending on the configuration

180

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Preliminary

LM3S6965 Microcontroller

Table 9-2. GPIO Interrupt Configuration Example

Register

Desired

Pin 2 Bit Valuea

 

 

 

 

 

 

 

Interrupt

7

6

5

4

3

2

1

0

 

Event

 

 

 

 

 

 

 

 

 

 

Trigger

 

 

 

 

 

 

 

 

GPIOIS

0=edge

X

X

X

X

X

0

X

X

 

1=level

 

 

 

 

 

 

 

 

GPIOIBE

0=single

X

X

X

X

X

0

X

X

 

edge

 

 

 

 

 

 

 

 

 

1=both

 

 

 

 

 

 

 

 

 

edges

 

 

 

 

 

 

 

 

GPIOIEV

0=Low level,

X

X

X

X

X

1

X

X

 

or negative

 

 

 

 

 

 

 

 

 

edge

 

 

 

 

 

 

 

 

 

1=Highlevel,

 

 

 

 

 

 

 

 

 

or positive

 

 

 

 

 

 

 

 

 

edge

 

 

 

 

 

 

 

 

GPIOIM

0=masked

0

0

0

0

0

1

0

0

1=not masked

a. X=Ignored (don’t care bit)

9.3Register Map

Table 9-3 on page 182 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address:

GPIO Port A: 0x4000.4000

GPIO Port B: 0x4000.5000

GPIO Port C: 0x4000.6000

GPIO Port D: 0x4000.7000

GPIO Port E: 0x4002.4000

GPIO Port F: 0x4002.5000

GPIO Port G: 0x4002.6000

Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data.

Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F.

The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W.

The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port

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Preliminary

General-Purpose Input/Outputs (GPIOs)

is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0.

Table 9-3. GPIO Register Map

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x000

GPIODATA

R/W

0x0000.0000

GPIO Data

184

0x400

GPIODIR

R/W

0x0000.0000

GPIO Direction

185

0x404

GPIOIS

R/W

0x0000.0000

GPIO Interrupt Sense

186

0x408

GPIOIBE

R/W

0x0000.0000

GPIO Interrupt Both Edges

187

0x40C

GPIOIEV

R/W

0x0000.0000

GPIO Interrupt Event

188

0x410

GPIOIM

R/W

0x0000.0000

GPIO Interrupt Mask

189

0x414

GPIORIS

RO

0x0000.0000

GPIO Raw Interrupt Status

190

0x418

GPIOMIS

RO

0x0000.0000

GPIO Masked Interrupt Status

191

0x41C

GPIOICR

W1C

0x0000.0000

GPIO Interrupt Clear

192

0x420

GPIOAFSEL

R/W

-

GPIO Alternate Function Select

193

0x500

GPIODR2R

R/W

0x0000.00FF

GPIO 2-mA Drive Select

195

0x504

GPIODR4R

R/W

0x0000.0000

GPIO 4-mA Drive Select

196

0x508

GPIODR8R

R/W

0x0000.0000

GPIO 8-mA Drive Select

197

0x50C

GPIOODR

R/W

0x0000.0000

GPIO Open Drain Select

198

0x510

GPIOPUR

R/W

-

GPIO Pull-Up Select

199

0x514

GPIOPDR

R/W

0x0000.0000

GPIO Pull-Down Select

200

0x518

GPIOSLR

R/W

0x0000.0000

GPIO Slew Rate Control Select

201

0x51C

GPIODEN

R/W

-

GPIO Digital Enable

202

0x520

GPIOLOCK

R/W

0x0000.0001

GPIO Lock

203

0x524

GPIOCR

-

-

GPIO Commit

204

0xFD0

GPIOPeriphID4

RO

0x0000.0000

GPIO Peripheral Identification 4

206

0xFD4

GPIOPeriphID5

RO

0x0000.0000

GPIO Peripheral Identification 5

207

0xFD8

GPIOPeriphID6

RO

0x0000.0000

GPIO Peripheral Identification 6

208

0xFDC

GPIOPeriphID7

RO

0x0000.0000

GPIO Peripheral Identification 7

209

0xFE0

GPIOPeriphID0

RO

0x0000.0061

GPIO Peripheral Identification 0

210

0xFE4

GPIOPeriphID1

RO

0x0000.0000

GPIO Peripheral Identification 1

211

0xFE8

GPIOPeriphID2

RO

0x0000.0018

GPIO Peripheral Identification 2

212

0xFEC

GPIOPeriphID3

RO

0x0000.0001

GPIO Peripheral Identification 3

213

0xFF0

GPIOPCellID0

RO

0x0000.000D

GPIO PrimeCell Identification 0

214

182

November 16, 2008

Preliminary

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