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БЭМЗ полищук доки / Склад / Datasheet_LM3S6965.pdf
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LM3S6965 Microcontroller

Figure 9-1. GPIO Port Block Diagram

Commit

 

Mode

Control

 

Control

 

 

GPIOLOCK

GPIOAFSEL

 

 

 

 

 

GPIOCR

 

 

 

 

 

 

 

 

 

 

Alternate Input

 

DEMUX

Pad Input

 

 

Alternate Output

 

 

 

 

 

 

 

 

 

 

 

 

Alternate Output Enable

 

 

 

 

 

 

 

GPIO Input

MUX

Pad Output

Digital

Package I/O Pin

 

Data

 

I/O Pad

 

 

 

 

 

 

 

 

Control

GPIO Output

 

 

 

 

 

 

 

 

 

 

 

GPIODATA

GPIO Output Enable

MUX

Pad Output Enable

 

 

 

GPIODIR

 

 

 

 

 

 

 

 

 

 

Interrupt

Pad

 

 

 

 

 

Control

Control

 

 

 

 

Interrupt

GPIOIS

GPIODR2R

 

 

 

 

GPIOIBE

GPIODR4R

 

 

 

 

 

 

 

 

 

 

GPIOIEV

GPIODR8R

 

 

 

 

 

GPIOIM

GPIOSLR

 

 

 

 

 

GPIORIS

GPIOPUR

 

 

 

 

 

GPIOMIS

GPIOPDR

 

 

 

 

 

GPIOICR

GPIOODR

 

 

 

 

 

 

GPIODEN

 

 

 

 

Identification Registers

GPIOPeriphID0 GPIOPeriphID4 GPIOPCellID0

GPIOPeriphID1 GPIOPeriphID5 GPIOPCellID1

GPIOPeriphID2 GPIOPeriphID6 GPIOPCellID2

GPIOPeriphID3 GPIOPeriphID7 GPIOPCellID3

9.1.1Data Control

ThedatacontrolregistersallowsoftwaretoconfiguretheoperationalmodesoftheGPIOs. Thedata directionregisterconfigurestheGPIOasaninputoranoutputwhilethedataregistereithercaptures incoming data or drives it out to the pads.

9.1.1.1Data Direction Operation

The GPIO Direction (GPIODIR) register (see page 185) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and thecorrespondingdataregisterbitwillcaptureandstorethevalueontheGPIOport. Whenthedata direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port.

9.1.1.2Data Register Operation

To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 184) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map.

November 16, 2008

177

Preliminary

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