LM3S6965 Microcontroller
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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PMISC |
AMISC |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
R/W1C |
R/W1C |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:2 |
reserved |
RO |
0x0 |
Software should not rely on the value of a reserved bit. To provide |
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
1 |
PMISC |
R/W1C |
0 |
Programming Masked Interrupt Status and Clear |
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This bit indicates whether an interrupt was signaled because a |
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programming cycle completed and was not masked. This bit is cleared |
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bywritinga1. The PRIS bitinthe FCRIS register(seepage161)isalso |
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cleared when the PMISC bit is cleared. |
0 |
AMISC |
R/W1C |
0 |
Access Masked Interrupt Status and Clear |
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Thisbitindicateswhetheraninterruptwassignaledbecauseanimproper |
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accesswasattemptedandwasnotmasked. Thisbitisclearedbywriting |
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a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC |
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bit is cleared. |
8.6Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000.
November 16, 2008 |
163 |
Preliminary
Internal Memory
Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
Thisregisterisprovidedasameansofcreatinga1-μstickdividerreloadvaluefortheflashcontroller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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USEC |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:8 |
reserved |
RO |
0x0 |
Software should not rely on the value of a reserved bit. To provide |
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compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
7:0 |
USEC |
R/W |
0x31 |
Microsecond Reload Value |
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MHz -1 of the controller clock when the flash is being erased or |
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programmed. |
If the maximum system frequency is being used, USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed.
164 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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READ_ENABLE |
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Type |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
Reset |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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READ_ENABLE |
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Type |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
Reset |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Bit/Field |
Name |
Type |
Reset |
Description |
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31:0 |
READ_ENABLE |
R/W |
0xFFFFFFFF |
Flash Read Enable |
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Enables 2-KB flash blocks to be executed or read. The policies may be |
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combinedasshowninthetable“FlashProtectionPolicyCombinations”. |
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Value |
Description |
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0xFFFFFFFF Enables 256 KB of flash. |
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November 16, 2008 |
165 |
Preliminary
Internal Memory
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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PROG_ENABLE |
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Type |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
Reset |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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PROG_ENABLE |
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Type |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
Reset |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Bit/Field |
Name |
Type |
Reset |
Description |
|
31:0 |
PROG_ENABLE |
R/W |
0xFFFFFFFF |
Flash Programming Enable |
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Configures 2-KB flash blocks to be execute only. The policies may be |
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combinedasshowninthetable“FlashProtectionPolicyCombinations”. |
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Value |
Description |
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0xFFFFFFFF Enables 256 KB of flash. |
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166 |
November 16, 2008 |
Preliminary