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LM3S6965 Microcontroller

Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C

Thisregisterindicatesthattheflashcontrollerhasaninterruptcondition. Aninterruptisonlysignaled if the corresponding FCIM register bit is set.

Flash Controller Raw Interrupt Status (FCRIS)

Base 0x400F.D000

Offset 0x00C

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

PRIS

ARIS

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

PRIS

RO

0

Programming Raw Interrupt Status

 

 

 

 

This bit indicates the current state of the programming cycle. If set, the

 

 

 

 

programming cycle completed; if cleared, the programming cycle has

 

 

 

 

not completed. Programming cycles are either write or erase actions

 

 

 

 

generated through the Flash Memory Control (FMC) register bits (see

 

 

 

 

page 159).

0

ARIS

RO

0

Access Raw Interrupt Status

 

 

 

 

Thisbitindicatesiftheflashwasimproperlyaccessed. Ifset,theprogram

 

 

 

 

triedtoaccesstheflashcountertothepolicyassetinthe Flash Memory

 

 

 

 

Protection Read Enable (FMPREn) and Flash Memory Protection

 

 

 

 

Program Enable (FMPPEn) registers. Otherwise, no access has tried

 

 

 

 

to improperly access the flash.

November 16, 2008

161

Preliminary

Internal Memory

Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010

This register controls whether the flash controller generates interrupts to the controller.

Flash Controller Interrupt Mask (FCIM)

Base 0x400F.D000

Offset 0x010

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

PMASK

AMASK

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

PMASK

R/W

0

Programming Interrupt Mask

 

 

 

 

This bit controls the reporting of the programming raw interrupt status

 

 

 

 

to the controller. If set, a programming-generated interrupt is promoted

 

 

 

 

tothecontroller. Otherwise,interruptsarerecordedbutsuppressedfrom

 

 

 

 

the controller.

0

AMASK

R/W

0

Access Interrupt Mask

 

 

 

 

This bit controls the reporting of the access raw interrupt status to the

 

 

 

 

controller. If set, an access-generated interrupt is promoted to the

 

 

 

 

controller. Otherwise, interrupts are recorded but suppressed from the

 

 

 

 

controller.

162

November 16, 2008

Preliminary

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