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Internal Memory

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x00C

FCRIS

RO

0x0000.0000

Flash Controller Raw Interrupt Status

161

0x010

FCIM

R/W

0x0000.0000

Flash Controller Interrupt Mask

162

0x014

FCMISC

R/W1C

0x0000.0000

Flash Controller Masked Interrupt Status and Clear

163

Flash Registers (System Control Offset)

 

 

 

0x130

FMPRE0

R/W

0xFFFF.FFFF

Flash Memory Protection Read Enable 0

165

0x200

FMPRE0

R/W

0xFFFF.FFFF

Flash Memory Protection Read Enable 0

165

0x134

FMPPE0

R/W

0xFFFF.FFFF

Flash Memory Protection Program Enable 0

166

0x400

FMPPE0

R/W

0xFFFF.FFFF

Flash Memory Protection Program Enable 0

166

0x140

USECRL

R/W

0x31

USec Reload

164

0x1D0

USER_DBG

R/W

0xFFFF.FFFE

User Debug

167

0x1E0

USER_REG0

R/W

0xFFFF.FFFF

User Register 0

168

0x1E4

USER_REG1

R/W

0xFFFF.FFFF

User Register 1

169

0x204

FMPRE1

R/W

0xFFFF.FFFF

Flash Memory Protection Read Enable 1

170

0x208

FMPRE2

R/W

0xFFFF.FFFF

Flash Memory Protection Read Enable 2

171

0x20C

FMPRE3

R/W

0xFFFF.FFFF

Flash Memory Protection Read Enable 3

172

0x404

FMPPE1

R/W

0xFFFF.FFFF

Flash Memory Protection Program Enable 1

173

0x408

FMPPE2

R/W

0xFFFF.FFFF

Flash Memory Protection Program Enable 2

174

0x40C

FMPPE3

R/W

0xFFFF.FFFF

Flash Memory Protection Program Enable 3

175

8.5Flash Register Descriptions (Flash Control Offset)

This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000.

156

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Preliminary

LM3S6965 Microcontroller

Register 1: Flash Memory Address (FMA), offset 0x000

During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable.

Flash Memory Address (FMA)

Base 0x400F.D000

Offset 0x000

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

OFFSET

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

OFFSET

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:18

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

17:0

OFFSET

R/W

0x0

Address Offset

 

 

 

 

Address offset in flash where operation is performed, except for

 

 

 

 

nonvolatileregisters(see“NonvolatileRegisterProgramming”onpage

 

 

 

 

154 for details on values for this field).

November 16, 2008

157

Preliminary

Internal Memory

Register 2: Flash Memory Data (FMD), offset 0x004

This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles.

Flash Memory Data (FMD)

Base 0x400F.D000

Offset 0x004

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:0

DATA

R/W

0x0

Data Value

 

 

 

 

Data value for write operation.

158

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 3: Flash Memory Control (FMC), offset 0x008

Whenthisregisteriswritten,theflashcontrollerinitiatestheappropriateaccesscycleforthelocation specified by the Flash Memory Address (FMA) register (see page 157). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 158) is written.

This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits.

It is a programming error to write multiple control bits and the results of such an operation are unpredictable.

Flash Memory Control (FMC)

Base 0x400F.D000

Offset 0x008

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

WRKEY

 

 

 

 

 

 

 

Type

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

COMT

MERASE

ERASE

WRITE

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

WRKEY

WO

0x0

Flash Write Key

 

 

 

 

This field contains a write key, which is used to minimize the incidence

 

 

 

 

of accidental flash writes. The value 0xA442 must be written into this

 

 

 

 

field for a write to occur. Writes to the FMC register without this WRKEY

 

 

 

 

value are ignored. A read of this field returns the value 0.

15:4

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

COMT

R/W

0

Commit Register Value

 

 

 

 

Commit (write) of register value to nonvolatile storage. A write of 0 has

 

 

 

 

no effect on the state of this bit.

 

 

 

 

If read, the state of the previous commit access is provided. If the

 

 

 

 

previous commit access is complete, a 0 is returned; otherwise, if the

 

 

 

 

commit access is not complete, a 1 is returned.

 

 

 

 

This can take up to 50 μs.

2

MERASE

R/W

0

Mass Erase Flash Memory

 

 

 

 

If this bit is set, the flash main memory of the device is all erased. A

 

 

 

 

write of 0 has no effect on the state of this bit.

If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned.

This can take up to 250 ms.

November 16, 2008

159

Preliminary

Internal Memory

Bit/Field

Name

Type

Reset

Description

1

ERASE

R/W

0

Erase a Page of Flash Memory

 

 

 

 

If this bit is set, the page of flash main memory as specified by the

 

 

 

 

contents of FMA is erased. A write of 0 has no effect on the state of this

 

 

 

 

bit.

 

 

 

 

Ifread,thestateofthepreviouseraseaccessisprovided. Iftheprevious

 

 

 

 

erase access is complete, a 0 is returned; otherwise, if the previous

 

 

 

 

erase access is not complete, a 1 is returned.

 

 

 

 

This can take up to 25 ms.

0

WRITE

R/W

0

Write a Word into Flash Memory

 

 

 

 

If this bit is set, the data stored in FMD is written into the location as

 

 

 

 

specified by the contents of FMA. A write of 0 has no effect on the state

 

 

 

 

of this bit.

Ifread,thestateofthepreviouswriteupdateisprovided. Iftheprevious write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned.

This can take up to 50 µs.

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November 16, 2008

Preliminary

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