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LM3S6965 Microcontroller

in the FMC register to activate a write operation. For the USER_DBG register, the data to be written must be loaded into the FMD register before it is "committed". All other registers are R/W and can have their operation tried before committing them to nonvolatile memory.

Important: These registers can only have bits changed from 1 to 0 by user programming, but can be restored to their factory default values by performing the sequence described in the sectioncalled“Recoveringa"Locked"Device”onpage60. Themasseraseofthemain flash array caused by the sequence is performed prior to restoring these registers.

In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective registers to indicate that they are available for user write. These three registers can only be written once whereas the flash protection registers may be written multiple times. Table 8-2 on page 155 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.

After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete.

Table 8-2. Flash Resident Registersa

Register to be Committed

FMA Value

Data Source

FMPRE0

0x0000.0000

FMPRE0

FMPRE1

0x0000.0002

FMPRE1

FMPRE2

0x0000.0004

FMPRE2

FMPRE3

0x0000.0006

FMPRE3

FMPPE0

0x0000.0001

FMPPE0

FMPPE1

0x0000.0003

FMPPE1

FMPPE2

0x0000.0005

FMPPE2

FMPPE3

0x0000.0007

FMPPE3

USER_REG0

0x8000.0000

USER_REG0

USER_REG1

0x8000.0001

USER_REG1

USER_DBG

0x7510.0000

FMD

a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device.

8.4Register Map

Table8-3onpage155liststheFlashmemoryandcontrolregisters. Theoffsetlistedisahexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System Control base address of 0x400F.E000.

Table 8-3. Flash Register Map

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

Flash Registers (Flash Control Offset)

 

 

 

0x000

FMA

R/W

0x0000.0000

Flash Memory Address

157

0x004

FMD

R/W

0x0000.0000

Flash Memory Data

158

0x008

FMC

R/W

0x0000.0000

Flash Memory Control

159

November 16, 2008

155

Preliminary

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