LM3S6965 Microcontroller

With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000.

For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual.

8.2.2Flash Memory

The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannotbeerasedorprogrammed,andcanonlybereadbythecontrollerinstructionfetchmechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.

See also “Serial Flash Loader” on page 589 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface.

8.2.2.1Flash Memory Timing

The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the

USec Reload (USECRL) register.

Onreset,the USECRL registerisloadedwithavaluethatconfigurestheflashtimingsothatitworks with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register.

8.2.2.2Flash Memory Protection

The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers.

■Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed.

■Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read bysoftwareordebuggers. Ifcleared,theblockmayonlybeexecutedandcontentsofthememory block are prohibited from being accessed as data.

The policies may be combined as shown in Table 8-1 on page 153.

Table 8-1. Flash Protection Policy Combinations

FMPPEnFMPREnProtection

00 Execute-onlyprotection. Theblockmayonlybeexecutedandmaynotbewrittenorerased. Thismode is used to protect code.

Preliminary