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LM3S6965 Microcontroller

Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018

This register is the raw interrupt status for the Hibernation module interrupt sources.

Hibernation Raw Interrupt Status (HIBRIS)

Base 0x400F.C000

Offset 0x018

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

EXTW

LOWBAT RTCALT1 RTCALT0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x000.0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

EXTW

RO

0

External Wake-Up Raw Interrupt Status

2

LOWBAT

RO

0

Low Battery Voltage Raw Interrupt Status

1

RTCALT1

RO

0

RTC Alert1 Raw Interrupt Status

0

RTCALT0

RO

0

RTC Alert0 Raw Interrupt Status

November 16, 2008

147

Preliminary

Hibernation Module

Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C

This register is the masked interrupt status for the Hibernation module interrupt sources.

Hibernation Masked Interrupt Status (HIBMIS)

Base 0x400F.C000

Offset 0x01C

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

EXTW

LOWBAT RTCALT1 RTCALT0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x000.0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

EXTW

RO

0

External Wake-Up Masked Interrupt Status

2

LOWBAT

RO

0

Low Battery Voltage Masked Interrupt Status

1

RTCALT1

RO

0

RTC Alert1 Masked Interrupt Status

0

RTCALT0

RO

0

RTC Alert0 Masked Interrupt Status

148

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020

Thisregisteristheinterruptwrite-one-to-clearregisterfortheHibernationmoduleinterruptsources.

Hibernation Interrupt Clear (HIBIC)

Base 0x400F.C000

Offset 0x020

Type R/W1C, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

EXTW

LOWBAT RTCALT1 RTCALT0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W1C

R/W1C

R/W1C

R/W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x000.0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

EXTW

R/W1C

0

External Wake-Up Masked Interrupt Clear

 

 

 

 

Reads return an indeterminate value.

2

LOWBAT

R/W1C

0

Low Battery Voltage Masked Interrupt Clear

 

 

 

 

Reads return an indeterminate value.

1

RTCALT1

R/W1C

0

RTC Alert1 Masked Interrupt Clear

 

 

 

 

Reads return an indeterminate value.

0

RTCALT0

R/W1C

0

RTC Alert0 Masked Interrupt Clear

 

 

 

 

Reads return an indeterminate value.

November 16, 2008

149

Preliminary

Hibernation Module

Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024

This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Hibernation RTC Trim (HIBRTCT)

Base 0x400F.C000

Offset 0x024

Type R/W, reset 0x0000.7FFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

TRIM

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

TRIM

R/W

0x7FFF

RTC Trim Value

 

 

 

 

ThisvalueisloadedintotheRTCpredividerevery64seconds. Itisused

 

 

 

 

to adjust the RTC rate to account for drift and inaccuracy in the clock

 

 

 

 

source. The compensation is made by software by adjusting the default

 

 

 

 

value of 0x7FFF up or down.

150

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C

This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the systemprocessorinordertostoreanynon-volatilestatedataandwillnotlosepowerduringapower cut operation.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Hibernation Data (HIBDATA)

Base 0x400F.C000

Offset 0x030-0x12C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

RTD

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

RTD

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:0

RTD

R/W

0x0000.0000

Hibernation Module NV Registers[63:0]

November 16, 2008

151

Preliminary

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