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LM3S6965 Microcontroller

Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C

This register is the 32-bit value loaded into the RTC counter.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Hibernation RTC Load (HIBRTCLD)

Base 0x400F.C000

Offset 0x00C

Type R/W, reset 0xFFFF.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

RTCLD

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

RTCLD

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:0

RTCLD

R/W

0xFFFF.FFFF

RTC Load

A write loads the current value into the RTC counter (RTCC).

A read returns the 32-bit load value.

November 16, 2008

143

Preliminary

Hibernation Module

Register 5: Hibernation Control (HIBCTL), offset 0x010

This register is the control register for the Hibernation module.

Hibernation Control (HIBCTL)

Base 0x400F.C000

Offset 0x010

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

VABORT CLK32EN LOWBATEN PINWEN

RTCWEN

CLKSEL

HIBREQ

RTCEN

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7

VABORT

R/W

0

Power Cut Abort Enable

 

 

 

 

Value Description

0 Power cut occurs during a low-battery alert.

1 Power cut is aborted.

6

CLK32EN

R/W

0

Clocking Enable

Value Description

0 Disabled

1 Enabled

This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize.

5

LOWBATEN

R/W

0

Low Battery Monitoring Enable

Value Description

0 Disabled

1 Enabled

When set, low battery voltage detection is enabled (VBAT < VLOWBAT).

4

PINWEN

R/W

0

External

WAKE

Pin Enable

Value Description

0 Disabled

1 Enabled

When set, an external event on the WAKE pin will re-power the device.

144

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

3

RTCWEN

R/W

0

RTC Wake-up Enable

 

 

 

 

Value

Description

 

 

 

 

0

Disabled

 

 

 

 

1

Enabled

When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1.

2

CLKSEL

R/W

0

Hibernation Module Clock Select

Value Description

0 Use Divide by 128 output. Use this value for a 4.194304-MHz crystal.

1 Use raw output. Use this value for a 32.768-kHz oscillator.

1

HIBREQ

R/W

0

Hibernation Request

Value Description

0 Disabled

1 Hibernation initiated

After a wake-up event, this bit is cleared by hardware.

0

RTCEN

R/W

0

RTC Timer Enable

Value Description

0 Disabled

1 Enabled

November 16, 2008

145

Preliminary

Hibernation Module

Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014

This register is the interrupt mask register for the Hibernation module interrupt sources.

Hibernation Interrupt Mask (HIBIM)

Base 0x400F.C000

Offset 0x014

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

EXTW

LOWBAT RTCALT1 RTCALT0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x000.0000 Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

EXTW

R/W

0

External Wake-Up Interrupt Mask

 

 

 

 

Value

Description

 

 

 

 

0

Masked

 

 

 

 

1

Unmasked

2

LOWBAT

R/W

0

Low Battery Voltage Interrupt Mask

 

 

 

 

Value

Description

 

 

 

 

0

Masked

 

 

 

 

1

Unmasked

1

RTCALT1

R/W

0

RTC Alert1 Interrupt Mask

 

 

 

 

Value

Description

 

 

 

 

0

Masked

 

 

 

 

1

Unmasked

0

RTCALT0

R/W

0

RTC Alert0 Interrupt Mask

 

 

 

 

Value

Description

 

 

 

 

0

Masked

 

 

 

 

1

Unmasked

146

November 16, 2008

Preliminary

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