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LM3S6965 Microcontroller

Table 7-1. Hibernation Module Register Map

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x000

HIBRTCC

RO

0x0000.0000

Hibernation RTC Counter

140

0x004

HIBRTCM0

R/W

0xFFFF.FFFF

Hibernation RTC Match 0

141

0x008

HIBRTCM1

R/W

0xFFFF.FFFF

Hibernation RTC Match 1

142

0x00C

HIBRTCLD

R/W

0xFFFF.FFFF

Hibernation RTC Load

143

0x010

HIBCTL

R/W

0x0000.0000

Hibernation Control

144

0x014

HIBIM

R/W

0x0000.0000

Hibernation Interrupt Mask

146

0x018

HIBRIS

RO

0x0000.0000

Hibernation Raw Interrupt Status

147

0x01C

HIBMIS

RO

0x0000.0000

Hibernation Masked Interrupt Status

148

0x020

HIBIC

R/W1C

0x0000.0000

Hibernation Interrupt Clear

149

0x024

HIBRTCT

R/W

0x0000.7FFF

Hibernation RTC Trim

150

0x030-

HIBDATA

R/W

0x0000.0000

Hibernation Data

151

0x12C

7.5Register Descriptions

The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset.

November 16, 2008

139

Preliminary

Hibernation Module

Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000

This register is the current 32-bit value of the RTC counter.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Hibernation RTC Counter (HIBRTCC)

Base 0x400F.C000

Offset 0x000

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

RTCC

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

RTCC

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:0

RTCC

RO

0x0000.0000

RTC Counter

 

 

 

 

A read returns the 32-bit counter value. This register is read-only. To

 

 

 

 

change the value, use the HIBRTCLD register.

140

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004

This register is the 32-bit match 0 register for the RTC counter.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Hibernation RTC Match 0 (HIBRTCM0)

Base 0x400F.C000

Offset 0x004

Type R/W, reset 0xFFFF.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

RTCM0

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

RTCM0

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:0

RTCM0

R/W

0xFFFF.FFFF

RTC Match 0

A write loads the value into the RTC match register.

A read returns the current match value.

November 16, 2008

141

Preliminary

Hibernation Module

Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008

This register is the 32-bit match 1 register for the RTC counter.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Hibernation RTC Match 1 (HIBRTCM1)

Base 0x400F.C000

Offset 0x008

Type R/W, reset 0xFFFF.FFFF

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

RTCM1

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

RTCM1

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:0

RTCM1

R/W

0xFFFF.FFFF

RTC Match 1

A write loads the value into the RTC match register.

A read returns the current match value.

142

November 16, 2008

Preliminary

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