Hibernation Module

1.WritetherequiredRTCmatchvaluetooneoftheHIBRTCMn registersatoffset0x004or0x008.

2.Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

3.Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014.

4.Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.

7.3.3RTC Match/Wake-Up from Hibernation

Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module:

1.Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.

2.Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

3.Writeanydatatoberetainedduringpowercuttothe HIBDATA registeratoffsets0x030-0x12C.

4.Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010.

7.3.4External Wake-Up from Hibernation

Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller:

1.Writeanydatatoberetainedduringpowercuttothe HIBDATA registeratoffsets0x030-0x12C.

2.Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010.

7.3.5RTC/External Wake-Up from Hibernation

1.Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.

2.Write the required RTC load value to the HIBRTCLD register at offset 0x00C.

3.Writeanydatatoberetainedduringpowercuttothe HIBDATA registeratoffsets0x030-0x12C.

4.SettheRTCMatch/ExternalWake-Upandstartthehibernationsequencebywriting0x0000.005F to the HIBCTL register at offset 0x010.

7.4Register Map

Table7-1onpage139liststheHibernationregisters.AlladdressesgivenarerelativetotheHibernation Module base address at 0x400F.C000.

Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. See “Register Access Timing” on page 133.

Preliminary