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LM3S6965 Microcontroller

Register 27: Software Reset Control 0 (SRCR0), offset 0x040

Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.

Software Reset Control 0 (SRCR0)

Base 0x400F.E000

Offset 0x040

Type R/W, reset 0x00000000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

reserved

 

 

 

 

 

PWM

 

reserved

 

ADC

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

RO

RO

RO

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

HIB

reserved

WDT

 

reserved

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

RO

RO

R/W

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:21

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

20

PWM

R/W

0

PWM Reset Control

 

 

 

 

Reset control for PWM module.

19:17

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

16

ADC

R/W

0

ADC0 Reset Control

 

 

 

 

Reset control for SAR ADC module 0.

15:7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

HIB

R/W

0

HIB Reset Control

 

 

 

 

Reset control for the Hibernation module.

5:4

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

WDT

R/W

0

WDT Reset Control

 

 

 

 

Reset control for Watchdog unit.

2:0

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

127

Preliminary

System Control

Register 28: Software Reset Control 1 (SRCR1), offset 0x044

Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.

Software Reset Control 1 (SRCR1)

Base 0x400F.E000

Offset 0x044

Type R/W, reset 0x00000000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

reserved

 

 

COMP1

COMP0

 

reserved

 

TIMER3

TIMER2

TIMER1

TIMER0

Type

RO

RO

RO

RO

RO

RO

R/W

R/W

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

reserved

I2C1

reserved

I2C0

reserved

QEI1

QEI0

 

reserved

 

SSI0

reserved

UART2

UART1

UART0

Type

RO

R/W

RO

R/W

RO

RO

R/W

R/W

RO

RO

RO

R/W

RO

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:26

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

25

COMP1

R/W

0

Analog Comp 1 Reset Control

 

 

 

 

Reset control for analog comparator 1.

24

COMP0

R/W

0

Analog Comp 0 Reset Control

 

 

 

 

Reset control for analog comparator 0.

23:20

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

19

TIMER3

R/W

0

Timer 3 Reset Control

 

 

 

 

Reset control for General-Purpose Timer module 3.

18

TIMER2

R/W

0

Timer 2 Reset Control

 

 

 

 

Reset control for General-Purpose Timer module 2.

17

TIMER1

R/W

0

Timer 1 Reset Control

 

 

 

 

Reset control for General-Purpose Timer module 1.

16

TIMER0

R/W

0

Timer 0 Reset Control

 

 

 

 

Reset control for General-Purpose Timer module 0.

15

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

14

I2C1

R/W

0

I2C1 Reset Control

 

 

 

 

Reset control for I2C unit 1.

13

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

128

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

12

I2C0

R/W

0

I2C0 Reset Control

 

 

 

 

Reset control for I2C unit 0.

11:10

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

9

QEI1

R/W

0

QEI1 Reset Control

 

 

 

 

Reset control for QEI unit 1.

8

QEI0

R/W

0

QEI0 Reset Control

 

 

 

 

Reset control for QEI unit 0.

7:5

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

4

SSI0

R/W

0

SSI0 Reset Control

 

 

 

 

Reset control for SSI unit 0.

3

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

2

UART2

R/W

0

UART2 Reset Control

 

 

 

 

Reset control for UART unit 2.

1

UART1

R/W

0

UART1 Reset Control

 

 

 

 

Reset control for UART unit 1.

0

UART0

R/W

0

UART0 Reset Control

 

 

 

 

Reset control for UART unit 0.

November 16, 2008

129

Preliminary

System Control

Register 29: Software Reset Control 2 (SRCR2), offset 0x048

Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.

Software Reset Control 2 (SRCR2)

Base 0x400F.E000

Offset 0x048

Type R/W, reset 0x00000000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

reserved

EPHY0

reserved

EMAC0

 

 

 

 

 

reserved

 

 

 

 

 

Type

RO

R/W

RO

R/W

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

30

EPHY0

R/W

0

PHY0 Reset Control

 

 

 

 

Reset control for Ethernet PHY unit 0.

29

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

28

EMAC0

R/W

0

MAC0 Reset Control

 

 

 

 

Reset control for Ethernet MAC unit 0.

27:7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

GPIOG

R/W

0

Port G Reset Control

 

 

 

 

Reset control for GPIO Port G.

5

GPIOF

R/W

0

Port F Reset Control

 

 

 

 

Reset control for GPIO Port F.

4

GPIOE

R/W

0

Port E Reset Control

 

 

 

 

Reset control for GPIO Port E.

3

GPIOD

R/W

0

Port D Reset Control

 

 

 

 

Reset control for GPIO Port D.

2

GPIOC

R/W

0

Port C Reset Control

 

 

 

 

Reset control for GPIO Port C.

1

GPIOB

R/W

0

Port B Reset Control

 

 

 

 

Reset control for GPIO Port B.

130

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

0

GPIOA

R/W

0

Port A Reset Control

 

 

 

 

Reset control for GPIO Port A.

November 16, 2008

131

Preliminary

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