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LM3S6965 Microcontroller

Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118

This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes.

Sleep Mode Clock Gating Control Register 2 (SCGC2)

Base 0x400F.E000

Offset 0x118

Type R/W, reset 0x00000000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

reserved

EPHY0

reserved

EMAC0

 

 

 

 

 

reserved

 

 

 

 

 

Type

RO

R/W

RO

R/W

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

30

EPHY0

R/W

0

PHY0 Clock Gating Control

 

 

 

 

This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate

 

 

 

 

a bus fault.

29

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

28

EMAC0

R/W

0

MAC0 Clock Gating Control

 

 

 

 

This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate

 

 

 

 

a bus fault.

27:7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

123

Preliminary

System Control

Bit/Field

Name

Type

Reset

Description

6

GPIOG

R/W

0

Port G Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port G. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

5

GPIOF

R/W

0

Port F Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port F. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

4

GPIOE

R/W

0

Port E Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port E. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

3

GPIOD

R/W

0

Port D Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port D. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

2

GPIOC

R/W

0

Port C Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port C. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

1

GPIOB

R/W

0

Port B Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port B. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

0

GPIOA

R/W

0

Port A Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port A. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

124

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128

This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes.

Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)

Base 0x400F.E000

Offset 0x128

Type R/W, reset 0x00000000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

reserved

EPHY0

reserved

EMAC0

 

 

 

 

 

reserved

 

 

 

 

 

Type

RO

R/W

RO

R/W

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

30

EPHY0

R/W

0

PHY0 Clock Gating Control

 

 

 

 

This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate

 

 

 

 

a bus fault.

29

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

28

EMAC0

R/W

0

MAC0 Clock Gating Control

 

 

 

 

This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate

 

 

 

 

a bus fault.

27:7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

125

Preliminary

System Control

Bit/Field

Name

Type

Reset

Description

6

GPIOG

R/W

0

Port G Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port G. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

5

GPIOF

R/W

0

Port F Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port F. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

4

GPIOE

R/W

0

Port E Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port E. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

3

GPIOD

R/W

0

Port D Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port D. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

2

GPIOC

R/W

0

Port C Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port C. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

1

GPIOB

R/W

0

Port B Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port B. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

0

GPIOA

R/W

0

Port A Clock Gating Control

 

 

 

 

This bit controls the clock gating for Port A. If set, the unit receives a

 

 

 

 

clock and functions. Otherwise, the unit is unclocked and disabled. If

 

 

 

 

theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

126

November 16, 2008

Preliminary

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