Добавил:

ktotogdetotam Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Брестский государственный технический университет

Предмет:

[НЕСОРТИРОВАННОЕ]

Файл:

БЭМЗ полищук доки / Склад / Datasheet_LM3S6965.pdf

Скачиваний:

Добавлен:

21.12.2020

Размер:

6.13 Mб

Скачать

☆

►Содержание►

<<< < Предыдущая 29 30 31 32 33 34 35 36 37 38 39 4041 / 17841 42 43 44 45 46 47 48 49 50 51 52 53 > Следующая >>>

System Control

Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124

This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes.

Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)

Base 0x400F.E000

Offset 0x124

Type R/W, reset 0x00000000

	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			reserved				COMP1	COMP0		reserved			TIMER3	TIMER2	TIMER1	TIMER0
Type	RO	RO	RO	RO	RO	RO	R/W	R/W	RO	RO	RO	RO	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	reserved	I2C1	reserved	I2C0	reserved		QEI1	QEI0		reserved		SSI0	reserved	UART2	UART1	UART0
Type	RO	R/W	RO	R/W	RO	RO	R/W	R/W	RO	RO	RO	R/W	RO	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit/Field	Name	Type	Reset	Description
31:26	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
25	COMP1	R/W	0	Analog Comparator 1 Clock Gating
				Thisbitcontrolstheclockgatingforanalogcomparator1. Ifset,theunit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
24	COMP0	R/W	0	Analog Comparator 0 Clock Gating
				Thisbitcontrolstheclockgatingforanalogcomparator0. Ifset,theunit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
23:20	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
19	TIMER3	R/W	0	Timer 3 Clock Gating Control
				This bit controls the clock gating for General-Purpose Timer module 3.
				If set, the unit receives a clock and functions. Otherwise, the unit is
				unclocked and disabled. If the unit is unclocked, reads or writes to the
				unit will generate a bus fault.

118	November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field	Name	Type	Reset	Description
18	TIMER2	R/W	0	Timer 2 Clock Gating Control
				This bit controls the clock gating for General-Purpose Timer module 2.
				If set, the unit receives a clock and functions. Otherwise, the unit is
				unclocked and disabled. If the unit is unclocked, reads or writes to the
				unit will generate a bus fault.
17	TIMER1	R/W	0	Timer 1 Clock Gating Control
				This bit controls the clock gating for General-Purpose Timer module 1.
				If set, the unit receives a clock and functions. Otherwise, the unit is
				unclocked and disabled. If the unit is unclocked, reads or writes to the
				unit will generate a bus fault.
16	TIMER0	R/W	0	Timer 0 Clock Gating Control
				This bit controls the clock gating for General-Purpose Timer module 0.
				If set, the unit receives a clock and functions. Otherwise, the unit is
				unclocked and disabled. If the unit is unclocked, reads or writes to the
				unit will generate a bus fault.
15	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
14	I2C1	R/W	0	I2C1 Clock Gating Control
				ThisbitcontrolstheclockgatingforI2Cmodule1. Ifset,theunitreceives
				a clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
13	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
12	I2C0	R/W	0	I2C0 Clock Gating Control
				ThisbitcontrolstheclockgatingforI2Cmodule0. Ifset,theunitreceives
				a clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
11:10	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
9	QEI1	R/W	0	QEI1 Clock Gating Control
				This bit controls the clock gating for QEI module 1. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
8	QEI0	R/W	0	QEI0 Clock Gating Control
				This bit controls the clock gating for QEI module 0. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
7:5	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.

November 16, 2008

119

Preliminary

System Control

Bit/Field	Name	Type	Reset	Description
4	SSI0	R/W	0	SSI0 Clock Gating Control
				ThisbitcontrolstheclockgatingforSSImodule0. Ifset,theunitreceives
				a clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
3	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
2	UART2	R/W	0	UART2 Clock Gating Control
				This bit controls the clock gating for UART module 2. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
1	UART1	R/W	0	UART1 Clock Gating Control
				This bit controls the clock gating for UART module 1. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
0	UART0	R/W	0	UART0 Clock Gating Control
				This bit controls the clock gating for UART module 0. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.

120	November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108

This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes.

Run Mode Clock Gating Control Register 2 (RCGC2)

Base 0x400F.E000

Offset 0x108

Type R/W, reset 0x00000000

	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	reserved	EPHY0	reserved	EMAC0						reserved
Type	RO	R/W	RO	R/W	RO	RO	RO	RO	RO	RO	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					reserved					GPIOG	GPIOF	GPIOE	GPIOD	GPIOC	GPIOB	GPIOA
Type	RO	RO	RO	RO	RO	RO	RO	RO	RO	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit/Field	Name	Type	Reset	Description
31	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
30	EPHY0	R/W	0	PHY0 Clock Gating Control
				This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
29	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
28	EMAC0	R/W	0	MAC0 Clock Gating Control
				This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
				receives a clock and functions. Otherwise, the unit is unclocked and
				disabled. Iftheunitisunclocked,readsorwritestotheunitwillgenerate
				a bus fault.
27:7	reserved	RO	0	Software should not rely on the value of a reserved bit. To provide
				compatibility with future products, the value of a reserved bit should be
				preserved across a read-modify-write operation.
6	GPIOG	R/W	0	Port G Clock Gating Control
				This bit controls the clock gating for Port G. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

November 16, 2008

121

Preliminary

System Control

Bit/Field	Name	Type	Reset	Description
5	GPIOF	R/W	0	Port F Clock Gating Control
				This bit controls the clock gating for Port F. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
4	GPIOE	R/W	0	Port E Clock Gating Control
				This bit controls the clock gating for Port E. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
3	GPIOD	R/W	0	Port D Clock Gating Control
				This bit controls the clock gating for Port D. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
2	GPIOC	R/W	0	Port C Clock Gating Control
				This bit controls the clock gating for Port C. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
1	GPIOB	R/W	0	Port B Clock Gating Control
				This bit controls the clock gating for Port B. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.
0	GPIOA	R/W	0	Port A Clock Gating Control
				This bit controls the clock gating for Port A. If set, the unit receives a
				clock and functions. Otherwise, the unit is unclocked and disabled. If
				theunitisunclocked,readsorwritestotheunitwillgenerateabusfault.

122	November 16, 2008

Preliminary

<<< < Предыдущая 29 30 31 32 33 34 35 36 37 38 39 4041 / 17841 42 43 44 45 46 47 48 49 50 51 52 53 > Следующая >>>

Соседние файлы в папке Склад

#
21.12.20206.13 Mб10Datasheet_LM3S6965.pdf
#
21.12.2020365.71 Кб5FDCC1602D.pdf
#
21.12.20208.16 Mб9PIC18F8722.pdf
#
21.12.2020124.93 Кб3перечень элементов модуль управления.doc