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System Control

Register 17: Device Capabilities 4 (DC4), offset 0x01C

Thisregisterprovidesalistoffeaturesavailableinthesystem. TheStellarisfamilyusesthisregister formattoindicatetheavailabilityofthefollowingfamilyfeaturesinthespecificdevice:EthernetMAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register.

Device Capabilities 4 (DC4)

Base 0x400F.E000

Offset 0x01C

Type RO, reset 0x5000.007F

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

reserved

EPHY0

reserved

EMAC0

 

 

 

 

 

reserved

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

30

EPHY0

RO

1

Ethernet PHY0 Present

 

 

 

 

When set, indicates that Ethernet PHY module 0 is present.

29

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

28

EMAC0

RO

1

Ethernet MAC0 Present

 

 

 

 

When set, indicates that Ethernet MAC module 0 is present.

27:7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

GPIOG

RO

1

GPIO Port G Present

 

 

 

 

When set, indicates that GPIO Port G is present.

5

GPIOF

RO

1

GPIO Port F Present

 

 

 

 

When set, indicates that GPIO Port F is present.

4

GPIOE

RO

1

GPIO Port E Present

 

 

 

 

When set, indicates that GPIO Port E is present.

3

GPIOD

RO

1

GPIO Port D Present

 

 

 

 

When set, indicates that GPIO Port D is present.

2

GPIOC

RO

1

GPIO Port C Present

 

 

 

 

When set, indicates that GPIO Port C is present.

104

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

1

GPIOB

RO

1

GPIO Port B Present

 

 

 

 

When set, indicates that GPIO Port B is present.

0

GPIOA

RO

1

GPIO Port A Present

 

 

 

 

When set, indicates that GPIO Port A is present.

November 16, 2008

105

Preliminary

System Control

Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100

This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes.

Run Mode Clock Gating Control Register 0 (RCGC0)

Base 0x400F.E000

Offset 0x100

Type R/W, reset 0x00000040

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

reserved

 

 

 

 

 

PWM

 

reserved

 

ADC

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

RO

RO

RO

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

reserved

 

 

MAXADCSPD

reserved

HIB

reserved

WDT

 

reserved

 

Type

RO

RO

RO

RO

RO

RO

R/W

R/W

RO

R/W

RO

RO

R/W

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:21

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

20

PWM

R/W

0

PWM Clock Gating Control

 

 

 

 

This bit controls the clock gating for the PWM module. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. If the unit is unclocked, a read or write to the unit generates

 

 

 

 

a bus fault.

19:17

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

16

ADC

R/W

0

ADC0 Clock Gating Control

 

 

 

 

This bit controls the clock gating for SAR ADC module 0. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. If the unit is unclocked, a read or write to the unit generates

 

 

 

 

a bus fault.

15:10

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

106

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

9:8

MAXADCSPD

R/W

0

ADC Sample Speed

 

 

 

 

This field sets the rate at which the ADC samples data. You cannot set

 

 

 

 

the rate higher than the maximum rate. You can set the sample rate by

 

 

 

 

setting the MAXADCSPD bit as follows:

 

 

 

 

Value

Description

 

 

 

 

0x3

1M samples/second

 

 

 

 

0x2

500K samples/second

 

 

 

 

0x1

250K samples/second

 

 

 

 

0x0

125K samples/second

7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

HIB

R/W

0

HIB Clock Gating Control

 

 

 

 

This bit controls the clock gating for the Hibernation module. If set, the

 

 

 

 

unitreceivesaclockandfunctions. Otherwise,theunitisunclockedand

 

 

 

 

disabled.

5:4

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

WDT

R/W

0

WDT Clock Gating Control

 

 

 

 

This bit controls the clock gating for the WDT module. If set, the unit

 

 

 

 

receives a clock and functions. Otherwise, the unit is unclocked and

 

 

 

 

disabled. If the unit is unclocked, a read or write to the unit generates

 

 

 

 

a bus fault.

2:0

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

107

Preliminary

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