System Control
Register 15: Device Capabilities 2 (DC2), offset 0x014
Thisregisterprovidesalistoffeaturesavailableinthesystem. TheStellarisfamilyusesthisregister format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register isconsistentwiththeRCGC1,SCGC1,andDCGC1 clockcontrolregistersandtheSRCR1 software reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x030F.5317
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
|
|
reserved |
|
|
COMP1 |
COMP0 |
|
reserved |
|
TIMER3 |
TIMER2 |
TIMER1 |
TIMER0 |
||
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
reserved |
I2C1 |
reserved |
I2C0 |
reserved |
QEI1 |
QEI0 |
|
reserved |
|
SSI0 |
reserved |
UART2 |
UART1 |
UART0 |
|
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:26 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
25 |
COMP1 |
RO |
1 |
Analog Comparator 1 Present |
|
|
|
|
When set, indicates that analog comparator 1 is present. |
24 |
COMP0 |
RO |
1 |
Analog Comparator 0 Present |
|
|
|
|
When set, indicates that analog comparator 0 is present. |
23:20 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
19 |
TIMER3 |
RO |
1 |
Timer 3 Present |
|
|
|
|
When set, indicates that General-Purpose Timer module 3 is present. |
18 |
TIMER2 |
RO |
1 |
Timer 2 Present |
|
|
|
|
When set, indicates that General-Purpose Timer module 2 is present. |
17 |
TIMER1 |
RO |
1 |
Timer 1 Present |
|
|
|
|
When set, indicates that General-Purpose Timer module 1 is present. |
16 |
TIMER0 |
RO |
1 |
Timer 0 Present |
|
|
|
|
When set, indicates that General-Purpose Timer module 0 is present. |
15 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
14 |
I2C1 |
RO |
1 |
I2C Module 1 Present |
|
|
|
|
When set, indicates that I2C module 1 is present. |
100 November 16, 2008
Preliminary
LM3S6965 Microcontroller
Bit/Field |
Name |
Type |
Reset |
Description |
13 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
12 |
I2C0 |
RO |
1 |
I2C Module 0 Present |
|
|
|
|
When set, indicates that I2C module 0 is present. |
11:10 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
9 |
QEI1 |
RO |
1 |
QEI1 Present |
|
|
|
|
When set, indicates that QEI module 1 is present. |
8 |
QEI0 |
RO |
1 |
QEI0 Present |
|
|
|
|
When set, indicates that QEI module 0 is present. |
7:5 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
4 |
SSI0 |
RO |
1 |
SSI0 Present |
|
|
|
|
When set, indicates that SSI module 0 is present. |
3 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
2 |
UART2 |
RO |
1 |
UART2 Present |
|
|
|
|
When set, indicates that UART module 2 is present. |
1 |
UART1 |
RO |
1 |
UART1 Present |
|
|
|
|
When set, indicates that UART module 1 is present. |
0 |
UART0 |
RO |
1 |
UART0 Present |
|
|
|
|
When set, indicates that UART module 0 is present. |
November 16, 2008 |
101 |
Preliminary
System Control
Register 16: Device Capabilities 3 (DC3), offset 0x018
Thisregisterprovidesalistoffeaturesavailableinthesystem. TheStellarisfamilyusesthisregister format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x8F0F.87FF
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
32KHZ |
|
reserved |
|
CCP3 |
CCP2 |
CCP1 |
CCP0 |
|
reserved |
|
ADC3 |
ADC2 |
ADC1 |
ADC0 |
|
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
PWMFAULT |
|
reserved |
|
C1PLUS C1MINUS |
C0O |
C0PLUS C0MINUS |
PWM5 |
PWM4 |
PWM3 |
PWM2 |
PWM1 |
PWM0 |
|||
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Bit/Field |
Name |
Type |
Reset |
Description |
31 |
32KHZ |
RO |
1 |
32KHz Input Clock Available |
|
|
|
|
When set, indicates an even CCP pin is present and can be used as a |
|
|
|
|
32-KHz input clock. |
30:28 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
27 |
CCP3 |
RO |
1 |
CCP3 Pin Present |
|
|
|
|
When set, indicates that Capture/Compare/PWM pin 3 is present. |
26 |
CCP2 |
RO |
1 |
CCP2 Pin Present |
|
|
|
|
When set, indicates that Capture/Compare/PWM pin 2 is present. |
25 |
CCP1 |
RO |
1 |
CCP1 Pin Present |
|
|
|
|
When set, indicates that Capture/Compare/PWM pin 1 is present. |
24 |
CCP0 |
RO |
1 |
CCP0 Pin Present |
|
|
|
|
When set, indicates that Capture/Compare/PWM pin 0 is present. |
23:20 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
19 |
ADC3 |
RO |
1 |
ADC3 Pin Present |
|
|
|
|
When set, indicates that ADC pin 3 is present. |
18 |
ADC2 |
RO |
1 |
ADC2 Pin Present |
|
|
|
|
When set, indicates that ADC pin 2 is present. |
17 |
ADC1 |
RO |
1 |
ADC1 Pin Present |
|
|
|
|
When set, indicates that ADC pin 1 is present. |
102 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Bit/Field |
Name |
Type |
Reset |
Description |
16 |
ADC0 |
RO |
1 |
ADC0 Pin Present |
|
|
|
|
When set, indicates that ADC pin 0 is present. |
15 |
PWMFAULT |
RO |
1 |
PWM Fault Pin Present |
|
|
|
|
When set, indicates that the PWM Fault pin is present. |
14:11 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
10 |
C1PLUS |
RO |
1 |
C1+ Pin Present |
|
|
|
|
Whenset,indicatesthattheanalogcomparator1(+)inputpinispresent. |
9 |
C1MINUS |
RO |
1 |
C1Pin Present |
|
|
|
|
Whenset,indicatesthattheanalogcomparator1(-)inputpinispresent. |
8 |
C0O |
RO |
1 |
C0o Pin Present |
|
|
|
|
When set, indicates that the analog comparator 0 output pin is present. |
7 |
C0PLUS |
RO |
1 |
C0+ Pin Present |
|
|
|
|
Whenset,indicatesthattheanalogcomparator0(+)inputpinispresent. |
6 |
C0MINUS |
RO |
1 |
C0Pin Present |
|
|
|
|
Whenset,indicatesthattheanalogcomparator0(-)inputpinispresent. |
5 |
PWM5 |
RO |
1 |
PWM5 Pin Present |
|
|
|
|
When set, indicates that the PWM pin 5 is present. |
4 |
PWM4 |
RO |
1 |
PWM4 Pin Present |
|
|
|
|
When set, indicates that the PWM pin 4 is present. |
3 |
PWM3 |
RO |
1 |
PWM3 Pin Present |
|
|
|
|
When set, indicates that the PWM pin 3 is present. |
2 |
PWM2 |
RO |
1 |
PWM2 Pin Present |
|
|
|
|
When set, indicates that the PWM pin 2 is present. |
1 |
PWM1 |
RO |
1 |
PWM1 Pin Present |
|
|
|
|
When set, indicates that the PWM pin 1 is present. |
0 |
PWM0 |
RO |
1 |
PWM0 Pin Present |
|
|
|
|
When set, indicates that the PWM pin 0 is present. |
November 16, 2008 |
103 |
Preliminary