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LM3S6965 Microcontroller

Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064

This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 86).

The PLL frequency is calculated using the PLLCFG field values, as follows:

PLLFreq = OSCFreq * F / (R + 1)

XTAL to PLL Translation (PLLCFG)

Base 0x400F.E000

Offset 0x064

Type RO, reset -

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

reserved

 

 

 

 

F

 

 

 

 

 

 

R

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Bit/Field

Name

Type

Reset

Description

31:14

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

13:5

F

RO

-

PLL F Value

 

 

 

 

This field specifies the value supplied to the PLL’s F input.

4:0

R

RO

-

PLL R Value

 

 

 

 

This field specifies the value supplied to the PLL’s R input.

November 16, 2008

91

Preliminary

System Control

Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070

This register overrides the RCC equivalent register fields when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified.

The SYSDIV2 field is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. The PLL VCO frequency is 400 MHz.

Run-Mode Clock Configuration 2 (RCC2)

Base 0x400F.E000

Offset 0x070

Type R/W, reset 0x0780.2810

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

USERCC2

reserved

 

 

SYSDIV2

 

 

 

 

 

reserved

 

 

 

Type

R/W

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

reserved

PWRDN2

reserved

BYPASS2

 

reserved

 

 

OSCSRC2

 

 

reserved

 

Type

RO

RO

R/W

RO

R/W

RO

RO

RO

RO

R/W

R/W

R/W

RO

RO

RO

RO

Reset

0

0

1

0

1

0

0

0

0

0

0

1

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31

USERCC2

R/W

0

Use RCC2

 

 

 

 

When set, overrides the RCC register fields.

30:29

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

28:23

SYSDIV2

R/W

0x0F

System Clock Divisor

 

 

 

 

Specifies which divisor is used to generate the system clock from the

 

 

 

 

PLL output.

 

 

 

 

Thisfieldiswiderthanthe RCC register SYSDIV fieldinordertoprovide

 

 

 

 

additional divisor values. This permits the system clock to be run at

 

 

 

 

much lower frequencies during Deep Sleep mode. For example, where

 

 

 

 

the RCC register SYSDIV encoding of 1111 provides /16, the RCC2

 

 

 

 

register SYSDIV2 encoding of 111111 provides /64.

22:14

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

13

PWRDN2

R/W

1

Power-Down PLL

 

 

 

 

When set, powers down the PLL.

12

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

11

BYPASS2

R/W

1

Bypass PLL

 

 

 

 

When set, bypasses the PLL for the clock source.

92

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

10:7

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6:4

OSCSRC2

R/W

0x1

Oscillator Source

 

 

 

 

Selects the input source for the OSC. The values are:

 

 

 

 

Value

Description

 

 

 

 

0x0

MOSC

 

 

 

 

 

Main oscillator

 

 

 

 

0x1

IOSC

 

 

 

 

 

Internal oscillator

 

 

 

 

0x2

IOSC/4

 

 

 

 

 

Internal oscillator / 4

 

 

 

 

0x3

30 kHz

 

 

 

 

 

30-kHz internal oscillator

 

 

 

 

0x4

Reserved

 

 

 

 

0x5

Reserved

 

 

 

 

0x6

Reserved

 

 

 

 

0x7

32 kHz

 

 

 

 

 

32.768-kHz external oscillator

3:0

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

93

Preliminary

System Control

Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144

This register provides configuration information for the hardware control of Deep Sleep Mode.

Deep Sleep Clock Configuration (DSLPCLKCFG)

Base 0x400F.E000

Offset 0x144

Type R/W, reset 0x0780.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

reserved

 

 

 

DSDIVORIDE

 

 

 

 

 

reserved

 

 

 

Type

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

 

DSOSCSRC

 

 

reserved

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:29

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

28:23

DSDIVORIDE

R/W

0x0F

Divider Field Override

 

 

 

 

6-bit system divider field to override when Deep-Sleep occurs with PLL

 

 

 

 

running.

22:7

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6:4

DSOSCSRC

R/W

0x0

Clock Source

 

 

 

 

Specifies the clock source during Deep-Sleep mode.

 

 

 

 

Value

Description

 

 

 

 

0x0

MOSC

 

 

 

 

 

Use main oscillator as source.

 

 

 

 

0x1

IOSC

 

 

 

 

 

Use internal 12-MHz oscillator as source.

 

 

 

 

0x2

Reserved

 

 

 

 

0x3

30 kHz

 

 

 

 

 

Use 30-kHz internal oscillator as source.

 

 

 

 

0x4

Reserved

 

 

 

 

0x5

Reserved

 

 

 

 

0x6

Reserved

 

 

 

 

0x7

32 kHz

 

 

 

 

 

Use 32.768-kHz external oscillator as source.

3:0

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

94

November 16, 2008

Preliminary

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