System Control

If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 91). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency.

The Crystal Value field (XTAL) on page 86 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Anytimethe XTAL fieldchanges,thenewsettings are translated and the internal PLL settings are updated.

Toconfiguretheexternal32-kHzreal-timeoscillatorasthePLLinputreference,programthe OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7.

6.1.4.4PLL Modes

The PLL has two modes of operation: Normal and Power-Down

■Normal: The PLL multiplies the input clock reference and drives the output.

■Power-Down:MostofthePLLinternalcircuitryisdisabledandthePLLdoesnotdrivetheoutput. The modes are programmed using the RCC/RCC2 register fields (see page 86 and page 92).

6.1.4.5PLL Operation

IfaPLLconfigurationischanged,thePLLoutputfrequencyisunstableuntilitreconverges(relocks)

to the new setting. The time between the configuration change and relock is TREADY (see Table 23-7 on page 572). During the relock time, the affected PLL is not usable as a clock reference.

The PLL is changed by one of the following:

■Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.

■Change in the PLL from Power-Down to Normal mode.

A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep

the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)

before the RCC/RCC2 register is switched to use the PLL.

If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2

register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software canusemanymethodstoensurethatthesystemisclockedfromthemainPLL,includingperiodically

polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt.

6.1.5System Control

For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logicforeachperipheralorblockinthesystemwhilethecontrollerisinRun,Sleep,andDeep-Sleep mode, respectively.

There are four levels of operation for the device defined as:

Preliminary