List of Figures

Figure 1-1.

Stellaris® LM3S6965 Microcontroller High-Level Block Diagram .........................................

35

Figure 2-1.

CPU Block Diagram .........................................................................................................

44

Figure 2-2.

TPIU Block Diagram ........................................................................................................

45

Figure 5-1.

JTAG Module Block Diagram ............................................................................................

56

Figure 5-2.

Test Access Port State Machine .......................................................................................

59

Figure 5-3.

IDCODE Register Format .................................................................................................

65

Figure 5-4.

BYPASS Register Format ................................................................................................

65

Figure 5-5.

Boundary Scan Register Format .......................................................................................

65

Figure 6-1.

External Circuitry to Extend Reset ....................................................................................

68

Figure 6-2.

Power Architecture ..........................................................................................................

71

Figure 6-3.

Main Clock Tree ..............................................................................................................

73

Figure 7-1.

Hibernation Module Block Diagram .................................................................................

133

Figure 7-2.

Clock Source Using Crystal ............................................................................................

134

Figure 7-3.

Clock Source Using Dedicated Oscillator .........................................................................

135

Figure 8-1.

Flash Block Diagram ......................................................................................................

152

Figure 9-1.

GPIO Port Block Diagram ...............................................................................................

177

Figure 9-2.

GPIODATA Write Example .............................................................................................

178

Figure 9-3.

GPIODATA Read Example .............................................................................................

178

Figure 10-1.

GPTM Module Block Diagram ........................................................................................

219

Figure 10-2.

16-Bit Input Edge Count Mode Example ..........................................................................

223

Figure 10-3.

16-Bit Input Edge Time Mode Example ...........................................................................

224

Figure 10-4.

16-Bit PWM Mode Example ............................................................................................

225

Figure 11-1.

WDT Module Block Diagram ..........................................................................................

255

Figure 12-1.

ADC Module Block Diagram ...........................................................................................

279

Figure 12-2.

Differential Sampling Range, VIN_ODD = 1.5 V ..................................................................

282

Figure 12-3.

Differential Sampling Range, VIN_ODD = 0.75 V ................................................................

283

Figure 12-4.

Differential Sampling Range, VIN_ODD = 2.25 V ................................................................

283

Figure 12-5.

Internal Temperature Sensor Characteristic .....................................................................

284

Figure 13-1.

UART Module Block Diagram .........................................................................................

315

Figure 13-2.

UART Character Frame .................................................................................................

316

Figure 13-3.

IrDA Data Modulation .....................................................................................................

318

Figure 14-1.

SSI Module Block Diagram .............................................................................................

355

Figure 14-2.

TI Synchronous Serial Frame Format (Single Transfer) ....................................................

358

Figure 14-3.

TI Synchronous Serial Frame Format (Continuous Transfer) ............................................

358

Figure 14-4.

Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ......................................

359

Figure 14-5.

Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ..............................

359

Figure 14-6.

Freescale SPI Frame Format with SPO=0 and SPH=1 .....................................................

360

Figure 14-7.

Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ...........................

361

Figure 14-8.

Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ....................

361

Figure 14-9.

Freescale SPI Frame Format with SPO=1 and SPH=1 .....................................................

362

Figure 14-10.

MICROWIRE Frame Format (Single Frame) ....................................................................

363

Figure 14-11.

MICROWIRE Frame Format (Continuous Transfer) .........................................................

364

Figure 14-12.

MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................

364

Figure 15-1.

I2C Block Diagram .........................................................................................................

393

Figure 15-2.

I2C Bus Configuration ....................................................................................................

393

November 16, 2008

9

Figure 15-3.

START and STOP Conditions .........................................................................................

394

Figure 15-4.

Complete Data Transfer with a 7-Bit Address ...................................................................

394

Figure 15-5.

R/S Bit in First Byte ........................................................................................................

394

Figure 15-6.

Data Validity During Bit Transfer on the I2C Bus ...............................................................

395

Figure 15-7.

Master Single SEND ......................................................................................................

398

Figure 15-8.

Master Single RECEIVE .................................................................................................

399

Figure 15-9.

Master Burst SEND .......................................................................................................

400

Figure 15-10.

Master Burst RECEIVE ..................................................................................................

401

Figure 15-11.

Master Burst RECEIVE after Burst SEND ........................................................................

402

Figure 15-12.

Master Burst SEND after Burst RECEIVE ........................................................................

403

Figure 15-13.

Slave Command Sequence ............................................................................................

404

Figure 16-1.

Ethernet Controller .........................................................................................................

429

Figure 16-2.

Ethernet Controller Block Diagram ..................................................................................

429

Figure 16-3.

Ethernet Frame .............................................................................................................

430

Figure 17-1.

Analog Comparator Module Block Diagram .....................................................................

474

Figure 17-2.

Structure of Comparator Unit ..........................................................................................

475

Figure 17-3.

Comparator Internal Reference Structure ........................................................................

475

Figure 18-1.

PWM Unit Diagram ........................................................................................................

486

Figure 18-2.

PWM Module Block Diagram ..........................................................................................

487

Figure 18-3.

PWM Count-Down Mode ................................................................................................

488

Figure 18-4.

PWM Count-Up/Down Mode ..........................................................................................

488

Figure 18-5.

PWM Generation Example In Count-Up/Down Mode .......................................................

489

Figure 18-6.

PWM Dead-Band Generator ...........................................................................................

489

Figure 19-1.

QEI Block Diagram ........................................................................................................

523

Figure 19-2.

Quadrature Encoder and Velocity Predivider Operation ....................................................

524

Figure 20-1.

100-Pin LQFP Package Pin Diagram ..............................................................................

539

Figure 20-2.

108-Ball BGA Package Pin Diagram (Top View) ...............................................................

540

Figure 23-1.

Load Conditions ............................................................................................................

572

Figure 23-2.

JTAG Test Clock Input Timing .........................................................................................

574

Figure 23-3.

JTAG Test Access Port (TAP) Timing ..............................................................................

574

Figure 23-4.

JTAG TRST Timing ........................................................................................................

575

Figure 23-5.

External Reset Timing (RST) ..........................................................................................

575

Figure 23-6.

Power-On Reset Timing .................................................................................................

576

Figure 23-7.

Brown-Out Reset Timing ................................................................................................

576

Figure 23-8.

Software Reset Timing ...................................................................................................

576

Figure 23-9.

Watchdog Reset Timing .................................................................................................

576

Figure 23-10.

Hibernation Module Timing .............................................................................................

577

Figure 23-11.

SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ..............

579

Figure 23-12.

SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer .............................

579

Figure 23-13.

SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .................................................

580

Figure 23-14.

I2C Timing .....................................................................................................................

581

Figure 23-15.

External XTLP Oscillator Characteristics .........................................................................

583

Figure 24-1.

100-Pin LQFP Package ..................................................................................................

585

Figure 24-2.

108-Ball BGA Package ..................................................................................................

587

10

November 16, 2008

LM3S6965 Microcontroller

List of Tables

Table 1.

Revision History ..............................................................................................................

20

Table 2.

Documentation Conventions ............................................................................................

22

Table 3-1.

Memory Map ...................................................................................................................

49

Table 4-1.

Exception Types ..............................................................................................................

52

Table 4-2.

Interrupts ........................................................................................................................

53

Table 5-1.

JTAG Port Pins Reset State .............................................................................................

57

Table 5-2.

JTAG Instruction Register Commands ...............................................................................

62

Table 6-1.

System Control Register Map ...........................................................................................

76

Table 7-1.

Hibernation Module Register Map ...................................................................................

139

Table 8-1.

Flash Protection Policy Combinations .............................................................................

153

Table 8-2.

Flash Resident Registers ...............................................................................................

155

Table 8-3.

Flash Register Map ........................................................................................................

155

Table 9-1.

GPIO Pad Configuration Examples .................................................................................

180

Table 9-2.

GPIO Interrupt Configuration Example ............................................................................

181

Table 9-3.

GPIO Register Map .......................................................................................................

182

Table 10-1.

Available CCP Pins ........................................................................................................

219

Table 10-2.

16-Bit Timer With Prescaler Configurations .....................................................................

222

Table 10-3.

Timers Register Map ......................................................................................................

228

Table 11-1.

Watchdog Timer Register Map ........................................................................................

256

Table 12-1.

Samples and FIFO Depth of Sequencers ........................................................................

279

Table 12-2.

Differential Sampling Pairs .............................................................................................

281

Table 12-3.

ADC Register Map .........................................................................................................

285

Table 13-1.

UART Register Map .......................................................................................................

320

Table 14-1.

SSI Register Map ..........................................................................................................

365

Table 15-1.

Examples of I2C Master Timer Period versus Speed Mode ...............................................

396

Table 15-2.

Inter-Integrated Circuit (I2C) Interface Register Map .........................................................

405

Table 15-3.

Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................

410

Table 16-1.

TX & RX FIFO Organization ...........................................................................................

431

Table 16-2.

Ethernet Register Map ...................................................................................................

435

Table 17-1.

Internal Reference Voltage and ACREFCTL Field Values .................................................

475

Table 17-2.

Analog Comparators Register Map .................................................................................

477

Table 18-1.

PWM Register Map ........................................................................................................

491

Table 19-1.

QEI Register Map ..........................................................................................................

526

Table 21-1.

Signals by Pin Number ...................................................................................................

541

Table 21-2.

Signals by Signal Name .................................................................................................

545

Table 21-3.

Signals by Function, Except for GPIO .............................................................................

550

Table 21-4.

GPIO Pins and Alternate Functions .................................................................................

553

Table 21-5.

Signals by Pin Number ...................................................................................................

554

Table 21-6.

Signals by Signal Name .................................................................................................

559

Table 21-7.

Signals by Function, Except for GPIO .............................................................................

563

Table 21-8.

GPIO Pins and Alternate Functions .................................................................................

566

Table 22-1.

Temperature Characteristics ...........................................................................................

568

Table 22-2.

Thermal Characteristics .................................................................................................

568

Table 23-1.

Maximum Ratings ..........................................................................................................

569

Table 23-2.

Recommended DC Operating Conditions ........................................................................

569

Table 23-3.

LDO Regulator Characteristics .......................................................................................

570

November 16, 2008

11

Table 23-4.

Detailed Power Specifications ........................................................................................

571

Table 23-5.

Flash Memory Characteristics ........................................................................................

572

Table 23-6.

Hibernation Module DC Characteristics ...........................................................................

572

Table 23-7.

Phase Locked Loop (PLL) Characteristics .......................................................................

572

Table 23-8.

Clock Characteristics .....................................................................................................

573

Table 23-9.

Crystal Characteristics ...................................................................................................

573

Table 23-10.

JTAG Characteristics .....................................................................................................

573

Table 23-11.

Reset Characteristics .....................................................................................................

575

Table 23-12.

Hibernation Module AC Characteristics ...........................................................................

577

Table 23-13.

GPIO Characteristics .....................................................................................................

577

Table 23-14.

ADC Characteristics .......................................................................................................

578

Table 23-15.

SSI Characteristics ........................................................................................................

578

Table 23-16.

I2C Characteristics .........................................................................................................

580

Table 23-17.

100BASE-TX Transmitter Characteristics ........................................................................

581

Table 23-18.

100BASE-TX Transmitter Characteristics (informative) .....................................................

581

Table 23-19.

100BASE-TX Receiver Characteristics ............................................................................

581

Table 23-20.

10BASE-T Transmitter Characteristics ............................................................................

581

Table 23-21.

10BASE-T Transmitter Characteristics (informative) .........................................................

582

Table 23-22.

10BASE-T Receiver Characteristics ................................................................................

582

Table 23-23.

Isolation Transformers ...................................................................................................

582

Table 23-24.

Ethernet Reference Crystal ............................................................................................

583

Table 23-25.

External XTLP Oscillator Characteristics .........................................................................

583

Table 23-26.

Analog Comparator Characteristics .................................................................................

584

Table 23-27.

Analog Comparator Voltage Reference Characteristics ....................................................

584

Table C-1.

Part Ordering Information ...............................................................................................

614

12

November 16, 2008