LM3S6965 Microcontroller

6System Control

System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting.

6.1Functional Description

The System Control module provides the following capabilities:

■Device identification, see “Device Identification” on page 67

■Local control, such as reset (see “Reset Control” on page 67), power (see “Power Control” on page 70) and clock control (see “Clock Control” on page 71)

■System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 74

6.1.1Device Identification

Severalread-onlyregistersprovidesoftwarewithinformationonthemicrocontroller,suchasversion, partnumber,SRAMsize,flashsize,andotherfeatures. Seethe DID0, DID1,and DC0-DC4 registers.

6.1.2Reset Control

This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence.

6.1.2.1CMOD0 and CMOD1 Test-Mode Control Pins

Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground.

6.1.2.2Reset Sources

The controller has five sources of reset:

1.External reset input pin (RST) assertion, see “RST Pin Assertion” on page 67.

2.Power-on reset (POR), see “Power-On Reset (POR)” on page 68.

3.Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 68.

4.Software-initiated reset (with the software reset registers), see “Software Reset” on page 69.

5.A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 69.

After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR isthecause,andthenalltheotherbitsinthe RESC registerareclearedexceptforthePORindicator.

6.1.2.3RST Pin Assertion

Theexternalresetpin(RST)resetsthecontroller. Thisresetsthecoreandalltheperipheralsexcept the JTAG TAP controller (see “JTAG Interface” on page 55). The external reset sequence is as follows:

Preliminary

System Control

1.The external reset pin (RST) is asserted and then de-asserted.

2.The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for synchronization.

The external reset timing is shown in Figure 23-5 on page 575.

6.1.2.4Power-On Reset (POR)

The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit generatesaresetsignaltotheinternallogicwhenthepowersupplyrampreachesathresholdvalue (VTH). IftheapplicationonlyusesthePORcircuit,the RST inputneedstobeconnectedtothepower supply (VDD) through a pull-up resistor (1K to 10K Ω).

Thedevicemustbeoperatingwithinthespecifiedoperatingparametersatthepointwhentheon-chip power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within 10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset to hold the device in reset longer than the internal POR, the RST input may be used with the circuit as shown in Figure 6-1 on page 68.

Figure 6-1. External Circuitry to Extend Reset

Stellaris

The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off.

The Power-On Reset sequence is as follows:

1.The controller waits for the later of external reset (RST) or internal POR to go inactive.

2.The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution.

The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 23-6 on page 576.

Note: The power-on reset also resets the JTAG controller. An external reset does not.

6.1.2.5Brown-Out Reset (BOR)

A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software.

The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset.

Preliminary

LM3S6965 Microcontroller

Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset.

The brown-out reset is equivalent to an assertion of the external RST input and the reset is held activeuntiltheproperVDD levelisrestored. The RESC registercanbeexaminedintheresetinterrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover.

The internal Brown-Out Reset timing is shown in Figure 23-7 on page 576.

6.1.2.6Software Reset

Software can reset a specific peripheral or generate a reset to the entire system .

Peripheralscanbeindividuallyresetbysoftwareviathreeregistersthatcontrolresetsignalstoeach peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 74). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset.

The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows:

1.A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register.

2.An internal reset is asserted.

3.The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution.

The software-initiated system reset timing is shown in Figure 23-8 on page 576.

6.1.2.7Watchdog Timer Reset

The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out.

After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register,andthetimerresumescountingdownfromthatvalue. Ifthetimercounts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows:

1.The watchdog timer times out for the second time without being serviced.

2.An internal reset is asserted.

3.The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution.

Preliminary