JTAG Interface

for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:

1.Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states.

2.Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.

3.Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state.

5.3Initialization and Configuration

After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enablingthealternatefunctions,anyotherchangestotheGPIOpadconfigurationsonthefiveJTAG pins (PB7 andPC[3:0]) should be reverted to their default settings.

5.4Register Descriptions

There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registerswithintheJTAGcontrollerareallaccessedseriallythroughtheTAPController. Theregisters can be broken down into two main categories: Instruction Registers and Data Registers.

5.4.1Instruction Register (IR)

The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 62. A detailed explanation of each instruction, along with its associated Data Register, follows.

Table 5-2. JTAG Instruction Register Commands

62 November 16, 2008

Preliminary

LM3S6965 Microcontroller

5.4.1.1EXTEST Instruction

TheEXTESTinstructionisnotassociatedwithitsownDataRegisterchain. TheEXTESTinstruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOADinstruction. WhentheEXTESTinstructionispresentintheInstructionRegister, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. WhiletheEXTESTinstructionispresentintheInstructionRegister,theBoundaryScan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register.

5.4.1.2INTEST Instruction

The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOADinstruction. WhentheINTESTinstructionispresentintheInstructionRegister, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it isonlyobservable. WhiletheINTEXTinstructionispresentintheInstructionRegister,theBoundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register.

5.4.1.3SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. Thisinstructionsamplesthecurrentstateofthepadpinsforobservationandpreloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAPcontrollerenterstheCaptureDRstateduringthisinstruction,theinput,output,andoutput-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests.

Whilethesesamplesoftheinputs,outputs,andoutputenablesarebeingshiftedoutoftheBoundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 65 for more information.

5.4.1.4ABORT Instruction

The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug AccessPort(DAP). ShiftingtheproperdataintothisDataRegisterclearsvariouserrorbitsorinitiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 66 for more information.

Preliminary