JTAG Interface

5.2.4.1GPIO Functionality

When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.

It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] inthe GPIOAFSEL register. IftheuserdoesnotrequiretheJTAG/SWDportfordebugging or board-level testing, this provides five more GPIOs for use in the design.

Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controllerbeforetheJTAGpinfunctionalityswitches. Thismaylockthedebuggeroutofthepart. This canbeavoidedwithasoftwareroutinethatrestoresJTAGfunctionalitybasedonanexternalorsoftware trigger.

The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and

PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 193) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page203)hasbeenunlockedandtheappropriatebitsofthe GPIO Commit (GPIOCR) register(see page 204) have been set to 1.

Recovering a "Locked" Device

Note: Performing the sequence below causes the nonvolatile registers discussed in “Nonvolatile RegisterProgramming”onpage154toberestoredtotheirfactorydefaultvalues. Themass erase of the flash memory caused by the below sequence occurs prior to the nonvolatile registers being restored.

If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is:

1.Assert and hold the RST signal.

2.Perform the JTAG-to-SWD switch sequence.

3.Perform the SWD-to-JTAG switch sequence.

4.Perform the JTAG-to-SWD switch sequence.

5.Perform the SWD-to-JTAG switch sequence.

6.Perform the JTAG-to-SWD switch sequence.

7.Perform the SWD-to-JTAG switch sequence.

8.Perform the JTAG-to-SWD switch sequence.

9.Perform the SWD-to-JTAG switch sequence.

10.Perform the JTAG-to-SWD switch sequence.

Preliminary