Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
БЭМЗ полищук доки / Склад / Datasheet_LM3S6965.pdf
Скачиваний:
10
Добавлен:
21.12.2020
Размер:
6.13 Mб
Скачать

LM3S6965 Microcontroller

Figure 5-2. Test Access Port State Machine

Test Logic Reset

10

Run Test Idle

Select DR Scan

1

1

 

 

0

 

0

 

 

 

 

 

Capture DR

 

 

1

0

 

 

 

 

 

Shift DR

 

 

 

1

0

 

 

 

 

Exit 1 DR

1

 

 

0

 

 

 

 

Pause DR

 

 

 

1

0

 

 

 

 

Exit 2 DR

 

 

0

1

 

 

 

 

 

Update DR

 

 

1

0

 

Select IR Scan

1

0

 

Capture IR

 

1

 

0

 

Shift IR

 

1

0

 

Exit 1 IR

1

0

 

Pause IR

 

1

0

 

Exit 2 IR

 

0

 

1

 

Update IR

 

10

5.2.3Shift Registers

The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift registerchainsamplesspecificinformationduringtheTAPcontroller’sCAPTUREstatesandallows thisinformationtobeshiftedoutof TDO duringtheTAPcontroller’sSHIFTstates. Whilethesampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 62.

5.2.4Operational Considerations

There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below.

November 16, 2008

59

Preliminary

Соседние файлы в папке Склад