		LM3S6965 Microcontroller
Table of Contents
Revision History .............................................................................................................................		20
About This Document ....................................................................................................................		22
Audience ..............................................................................................................................................		22
About This Manual ................................................................................................................................		22
Related Documents ...............................................................................................................................		22
Documentation Conventions ..................................................................................................................		22
1	Architectural Overview ......................................................................................................	25
1.1	Product Features ......................................................................................................................	25
1.2	Target Applications ....................................................................................................................	34
1.3	High-Level Block Diagram .........................................................................................................	34
1.4	Functional Overview ..................................................................................................................	36
1.4.1	ARM Cortex™-M3 .....................................................................................................................	36
1.4.2	Motor Control Peripherals ..........................................................................................................	36
1.4.3	Analog Peripherals ....................................................................................................................	37
1.4.4	Serial Communications Peripherals ............................................................................................	38
1.4.5	System Peripherals ...................................................................................................................	39
1.4.6	Memory Peripherals ..................................................................................................................	40
1.4.7	Additional Features ...................................................................................................................	41
1.4.8	Hardware Details ......................................................................................................................	41
2	ARM Cortex-M3 Processor Core ......................................................................................	43
2.1	Block Diagram ..........................................................................................................................	44
2.2	Functional Description ...............................................................................................................	44
2.2.1	Serial Wire and JTAG Debug .....................................................................................................	44
2.2.2	Embedded Trace Macrocell (ETM) .............................................................................................	45
2.2.3	Trace Port Interface Unit (TPIU) .................................................................................................	45
2.2.4	ROM Table ...............................................................................................................................	45
2.2.5	Memory Protection Unit (MPU) ...................................................................................................	45
2.2.6	Nested Vectored Interrupt Controller (NVIC) ................................................................................	45
3	Memory Map .......................................................................................................................	49
4	Interrupts ............................................................................................................................	52
5	JTAG Interface ....................................................................................................................	55
5.1	Block Diagram ..........................................................................................................................	56
5.2	Functional Description ...............................................................................................................	56
5.2.1	JTAG Interface Pins ..................................................................................................................	56
5.2.2	JTAG TAP Controller .................................................................................................................	58
5.2.3	Shift Registers ..........................................................................................................................	59
5.2.4	Operational Considerations ........................................................................................................	59
5.3	Initialization and Configuration ...................................................................................................	62
5.4	Register Descriptions ................................................................................................................	62
5.4.1	Instruction Register (IR) .............................................................................................................	62
5.4.2	Data Registers ..........................................................................................................................	64
6	System Control ...................................................................................................................	67
6.1	Functional Description ...............................................................................................................	67
6.1.1	Device Identification ..................................................................................................................	67
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6.1.2	Reset Control ............................................................................................................................	67
6.1.3	Power Control ...........................................................................................................................	70
6.1.4	Clock Control ............................................................................................................................	71
6.1.5	System Control .........................................................................................................................	74
6.2	Initialization and Configuration ...................................................................................................	75
6.3	Register Map ............................................................................................................................	76
6.4	Register Descriptions ................................................................................................................	77

7	Hibernation Module ..........................................................................................................	132
7.1	Block Diagram ........................................................................................................................	133
7.2	Functional Description .............................................................................................................	133
7.2.1	Register Access Timing ...........................................................................................................	133
7.2.2	Clock Source ..........................................................................................................................	134
7.2.3	Battery Management ...............................................................................................................	135
7.2.4	Real-Time Clock ......................................................................................................................	135
7.2.5	Non-Volatile Memory ...............................................................................................................	136
7.2.6	Power Control .........................................................................................................................	136
7.2.7	Initiating Hibernate ..................................................................................................................	136
7.2.8	Interrupts and Status ...............................................................................................................	137
7.3	Initialization and Configuration .................................................................................................	137
7.3.1	Initialization .............................................................................................................................	137
7.3.2	RTC Match Functionality (No Hibernation) ................................................................................	137
7.3.3	RTC Match/Wake-Up from Hibernation .....................................................................................	138
7.3.4	External Wake-Up from Hibernation ..........................................................................................	138
7.3.5	RTC/External Wake-Up from Hibernation ..................................................................................	138
7.4	Register Map ..........................................................................................................................	138
7.5	Register Descriptions ..............................................................................................................	139

8	Internal Memory ...............................................................................................................	152
8.1	Block Diagram ........................................................................................................................	152
8.2	Functional Description .............................................................................................................	152
8.2.1	SRAM Memory ........................................................................................................................	152
8.2.2	Flash Memory .........................................................................................................................	153
8.3	Flash Memory Initialization and Configuration ...........................................................................	154
8.3.1	Flash Programming .................................................................................................................	154
8.3.2	Nonvolatile Register Programming ...........................................................................................	154
8.4	Register Map ..........................................................................................................................	155
8.5	Flash Register Descriptions (Flash Control Offset) .....................................................................	156
8.6	Flash Register Descriptions (System Control Offset) ..................................................................	163

9	General-Purpose Input/Outputs (GPIOs)	....................................................................... 176
9.1	Functional Description .............................................................................................................	176
9.1.1	Data Control ...........................................................................................................................	177
9.1.2	Interrupt Control ......................................................................................................................	178
9.1.3	Mode Control ..........................................................................................................................	179
9.1.4	Commit Control .......................................................................................................................	179
9.1.5	Pad Control .............................................................................................................................	179
9.1.6	Identification ...........................................................................................................................	180
9.2	Initialization and Configuration .................................................................................................	180
9.3	Register Map ..........................................................................................................................	181
9.4	Register Descriptions ..............................................................................................................	183
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		LM3S6965 Microcontroller
10	General-Purpose Timers .................................................................................................	218
10.1	Block Diagram ........................................................................................................................	219
10.2	Functional Description .............................................................................................................	220
10.2.1	GPTM Reset Conditions ..........................................................................................................	220
10.2.2	32-Bit Timer Operating Modes ..................................................................................................	220
10.2.3	16-Bit Timer Operating Modes ..................................................................................................	221
10.3	Initialization and Configuration .................................................................................................	225
10.3.1	32-Bit One-Shot/Periodic Timer Mode .......................................................................................	225
10.3.2	32-Bit Real-Time Clock (RTC) Mode .........................................................................................	226
10.3.3	16-Bit One-Shot/Periodic Timer Mode .......................................................................................	226
10.3.4	16-Bit Input Edge Count Mode .................................................................................................	227
10.3.5	16-Bit Input Edge Timing Mode ................................................................................................	227
10.3.6	16-Bit PWM Mode ...................................................................................................................	228
10.4	Register Map ..........................................................................................................................	228
10.5	Register Descriptions ..............................................................................................................	229
11	Watchdog Timer ...............................................................................................................	254
11.1	Block Diagram ........................................................................................................................	255
11.2	Functional Description .............................................................................................................	255
11.3	Initialization and Configuration .................................................................................................	256
11.4	Register Map ..........................................................................................................................	256
11.5	Register Descriptions ..............................................................................................................	257
12	Analog-to-Digital Converter (ADC) .................................................................................	278
12.1	Block Diagram ........................................................................................................................	278
12.2	Functional Description .............................................................................................................	279
12.2.1	Sample Sequencers ................................................................................................................	279
12.2.2	Module Control ........................................................................................................................	280
12.2.3	Hardware Sample Averaging Circuit .........................................................................................	281
12.2.4	Analog-to-Digital Converter ......................................................................................................	281
12.2.5	Differential Sampling ...............................................................................................................	281
12.2.6	Test Modes .............................................................................................................................	283
12.2.7	Internal Temperature Sensor ....................................................................................................	284
12.3	Initialization and Configuration .................................................................................................	284
12.3.1	Module Initialization .................................................................................................................	284
12.3.2	Sample Sequencer Configuration .............................................................................................	285
12.4	Register Map ..........................................................................................................................	285
12.5	Register Descriptions ..............................................................................................................	286
13	Universal Asynchronous Receivers/Transmitters (UARTs) .........................................	314
13.1	Block Diagram ........................................................................................................................	315
13.2	Functional Description .............................................................................................................	315
13.2.1	Transmit/Receive Logic ...........................................................................................................	315
13.2.2	Baud-Rate Generation .............................................................................................................	316
13.2.3	Data Transmission ..................................................................................................................	317
13.2.4	Serial IR (SIR) .........................................................................................................................	317
13.2.5	FIFO Operation .......................................................................................................................	318
13.2.6	Interrupts ................................................................................................................................	318
13.2.7	Loopback Operation ................................................................................................................	319
13.2.8	IrDA SIR block ........................................................................................................................	319
13.3	Initialization and Configuration .................................................................................................	319
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13.4	Register Map ..........................................................................................................................	320
13.5	Register Descriptions ..............................................................................................................	321

14	Synchronous Serial Interface (SSI) ................................................................................	355
14.1	Block Diagram ........................................................................................................................	355
14.2	Functional Description .............................................................................................................	355
14.2.1	Bit Rate Generation .................................................................................................................	356
14.2.2	FIFO Operation .......................................................................................................................	356
14.2.3	Interrupts ................................................................................................................................	356
14.2.4	Frame Formats .......................................................................................................................	357
14.3	Initialization and Configuration .................................................................................................	364
14.4	Register Map ..........................................................................................................................	365
14.5	Register Descriptions ..............................................................................................................	366
15	Inter-Integrated Circuit (I2C) Interface ............................................................................	392
15.1	Block Diagram ........................................................................................................................	393
15.2	Functional Description .............................................................................................................	393
15.2.1	I2C Bus Functional Overview ....................................................................................................	393
15.2.2	Available Speed Modes ...........................................................................................................	395
15.2.3	Interrupts ................................................................................................................................	396
15.2.4	Loopback Operation ................................................................................................................	397
15.2.5	Command Sequence Flow Charts ............................................................................................	397
15.3	Initialization and Configuration .................................................................................................	404
15.4	Register Map ..........................................................................................................................	405
15.5	Register Descriptions (I2C Master) ...........................................................................................	406
15.6	Register Descriptions (I2C Slave) .............................................................................................	419
16	Ethernet Controller ..........................................................................................................	428
16.1	Block Diagram ........................................................................................................................	428
16.2	Functional Description .............................................................................................................	429
16.2.1	MAC Operation .......................................................................................................................	429
16.2.2	Internal MII Operation ..............................................................................................................	433
16.2.3	PHY Operation ........................................................................................................................	433
16.2.4	Interrupts ................................................................................................................................	434
16.3	Initialization and Configuration .................................................................................................	434
16.4	Ethernet Register Map .............................................................................................................	435
16.5	Ethernet MAC Register Descriptions .........................................................................................	436
16.6	MII Management Register Descriptions .....................................................................................	454
17	Analog Comparators .......................................................................................................	473
17.1	Block Diagram ........................................................................................................................	474
17.2	Functional Description .............................................................................................................	474
17.2.1	Internal Reference Programming ..............................................................................................	475
17.3	Initialization and Configuration .................................................................................................	476
17.4	Register Map ..........................................................................................................................	476
17.5	Register Descriptions ..............................................................................................................	477
18	Pulse Width Modulator (PWM) ........................................................................................	485
18.1	Block Diagram ........................................................................................................................	486
18.2	Functional Description .............................................................................................................	487
18.2.1	PWM Timer .............................................................................................................................	487
18.2.2	PWM Comparators ..................................................................................................................	487
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LM3S6965 Microcontroller

18.2.3	PWM Signal Generator ............................................................................................................	488
18.2.4	Dead-Band Generator .............................................................................................................	489
18.2.5	Interrupt/ADC-Trigger Selector .................................................................................................	489
18.2.6	Synchronization Methods ........................................................................................................	490
18.2.7	Fault Conditions ......................................................................................................................	490
18.2.8	Output Control Block ...............................................................................................................	490
18.3	Initialization and Configuration .................................................................................................	490
18.4	Register Map ..........................................................................................................................	491
18.5	Register Descriptions ..............................................................................................................	493
19	Quadrature Encoder Interface (QEI) ...............................................................................	522
19.1	Block Diagram ........................................................................................................................	522
19.2	Functional Description .............................................................................................................	523
19.3	Initialization and Configuration .................................................................................................	525
19.4	Register Map ..........................................................................................................................	526
19.5	Register Descriptions ..............................................................................................................	526
20	Pin Diagram ......................................................................................................................	539
21	Signal Tables ....................................................................................................................	541
21.1	100-Pin LQFP Package Pin Tables ...........................................................................................	541
21.2	108-Pin BGA Package Pin Tables ............................................................................................	554
22	Operating Characteristics ...............................................................................................	568
23	Electrical Characteristics ................................................................................................	569
23.1	DC Characteristics ..................................................................................................................	569
23.1.1	Maximum Ratings ...................................................................................................................	569
23.1.2	Recommended DC Operating Conditions ..................................................................................	569
23.1.3	On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................	570
23.1.4	Power Specifications ...............................................................................................................	570
23.1.5	Flash Memory Characteristics ..................................................................................................	572
23.1.6	Hibernation .............................................................................................................................	572
23.2	AC Characteristics ...................................................................................................................	572
23.2.1	Load Conditions ......................................................................................................................	572
23.2.2	Clocks ....................................................................................................................................	572
23.2.3	JTAG and Boundary Scan ........................................................................................................	573
23.2.4	Reset .....................................................................................................................................	575
23.2.5	Hibernation Module .................................................................................................................	576
23.2.6	General-Purpose I/O (GPIO) ....................................................................................................	577
23.2.7	Analog-to-Digital Converter ......................................................................................................	578
23.2.8	Synchronous Serial Interface (SSI) ...........................................................................................	578
23.2.9	Inter-Integrated Circuit (I2C) Interface .......................................................................................	580
23.2.10	Ethernet Controller ..................................................................................................................	581
23.2.11	Analog Comparator .................................................................................................................	584
24	Package Information ........................................................................................................	585
A	Serial Flash Loader ..........................................................................................................	589
A.1	Serial Flash Loader .................................................................................................................	589
A.2	Interfaces ...............................................................................................................................	589
A.2.1	UART .....................................................................................................................................	589
A.2.2	SSI .........................................................................................................................................	589

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Table of Contents

A.3	Packet Handling ......................................................................................................................	590
A.3.1	Packet Format ........................................................................................................................	590
A.3.2	Sending Packets .....................................................................................................................	590
A.3.3	Receiving Packets ...................................................................................................................	590
A.4	Commands .............................................................................................................................	591
A.4.1	COMMAND_PING (0X20) ........................................................................................................	591
A.4.2	COMMAND_GET_STATUS (0x23) ...........................................................................................	591
A.4.3	COMMAND_DOWNLOAD (0x21) .............................................................................................	591
A.4.4	COMMAND_SEND_DATA (0x24) .............................................................................................	592
A.4.5	COMMAND_RUN (0x22) .........................................................................................................	592
A.4.6	COMMAND_RESET (0x25) .....................................................................................................	592
B	Register Quick Reference ...............................................................................................	594
C	Ordering and Contact Information .................................................................................	614
C.1	Ordering Information ................................................................................................................	614
C.2	Kits .........................................................................................................................................	614
C.3	Company Information ..............................................................................................................	615
C.4	Support Information .................................................................................................................	615

8	November 16, 2008

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