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LM3S6965 Microcontroller

23 Electrical Characteristics

23.1DC Characteristics

23.1.1Maximum Ratings

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device.

Note: The device is not guaranteed to operate properly at the maximum ratings.

Table 23-1. Maximum Ratings

Characteristic

Symbol

Value

Unit

a

 

Min Max

 

 

 

 

I/O supply voltage (VDD)

VDD

0

4

V

Core supply voltage (VDD25)

VDD25

0

3

V

Analog supply voltage (VDDA)

VDDA

0

4

V

Battery supply voltage (VBAT)

VBAT

0

4

V

Ethernet PHY supply voltage (VCCPHY)

VCCPHY

0

4

V

Input voltage

VIN

-0.3

5.5

V

Maximum current per output pins

I

-

25

mA

a. Voltages are measured with respect to GND.

Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD).

23.1.2Recommended DC Operating Conditions

For special high-current applications, the GPIO output buffers may be used with the following restrictions. WiththeGPIOpinsconfiguredas8-mAoutputdrivers,atotaloffourGPIOoutputsmay be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package.

Table 23-2. Recommended DC Operating Conditions

Parameter

Parameter Name

Min

Nom

Max

Unit

VDD

I/O supply voltage

3.0

3.3

3.6

V

VDD25

Core supply voltage

2.25

2.5

2.75

V

VDDA

Analog supply voltage

3.0

3.3

3.6

V

VBAT

Battery supply voltage

2.3

3.0

3.6

V

VCCPHY

Ethernet PHY supply voltage

3.0

3.3

3.6

V

VIH

High-level input voltage

2.0

-

5.0

V

VIL

Low-level input voltage

-0.3

-

1.3

V

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Electrical Characteristics

Parameter

Parameter Name

Min

Nom

Max

Unit

VSIH

High-level input voltage for Schmitt trigger inputs

0.8 * VDD

-

VDD

V

VSIL

Low-level input voltage for Schmitt trigger inputs

0

-

0.2 * VDD

V

VOHa

High-level output voltage

2.4

-

-

V

VOLa

Low-level output voltage

-

-

0.4

V

IOH

High-level source current, VOH=2.4 V

 

 

 

 

 

2-mA Drive

2.0

-

-

mA

 

4-mA Drive

4.0

-

-

mA

 

8-mA Drive

8.0

-

-

mA

IOL

Low-level sink current, VOL=0.4 V

 

 

 

 

 

2-mA Drive

2.0

-

-

mA

 

4-mA Drive

4.0

-

-

mA

 

8-mA Drive

8.0

-

-

mA

a. VOL and VOH shift to 1.2 V when using high-current GPIOs.

23.1.3On-Chip Low Drop-Out (LDO) Regulator Characteristics

Table 23-3. LDO Regulator Characteristics

Parameter

Parameter Name

Min

Nom Max Unit

VLDOOUT

Programmable internal (logic) power supply output value 2.25

2.5

2.75

V

 

Output voltage accuracy

-

2%

-

%

tPON

Power-on time

-

-

100

µs

tON

Time on

-

-

200

µs

tOFF

Time off

-

-

100

µs

VSTEP

Step programming incremental voltage

-

50

-

mV

CLDO

External filter capacitor size for internal power supply

1.0

-

3.0

µF

23.1.4Power Specifications

The power measurements specified in the tables that follow are run on the core processor using SRAM with the following specifications (except as noted):

VDD = 3.3 V

VDD25 = 2.50 V

VBAT = 3.0 V

VDDA = 3.3 V

VDDPHY = 3.3 V

Temperature = 25°C

Clock Source (MOSC) =3.579545 MHz Crystal Oscillator

Main oscillator (MOSC) = enabled

Internal oscillator (IOSC) = disabled

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Preliminary

LM3S6965 Microcontroller

Table 23-4. Detailed Power Specifications

Parameter

Parameter

Conditions

3.3 V VDD, VDDA,

2.5 V VDD25

3.0 V VBAT

Unit

 

Name

 

VDDPHY

 

 

 

 

 

 

 

 

Nom

Max

Nom

Max

Nom

Max

 

IDD_RUN

Run mode 1

VDD25 = 2.50 V

48

pendinga

108

pendinga

0

pendinga

mA

 

(Flash loop)

Code= while(1){} executed in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flash

 

 

 

 

 

 

 

 

 

Peripherals = All ON

 

 

 

 

 

 

 

 

 

System Clock = 50 MHz (with

 

 

 

 

 

 

 

 

 

PLL)

 

 

 

 

 

 

 

 

Run mode 2

VDD25 = 2.50 V

5

pendinga

52

pendinga

0

pendinga

mA

 

(Flash loop)

Code= while(1){} executed in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flash

 

 

 

 

 

 

 

 

 

Peripherals = All OFF

 

 

 

 

 

 

 

 

 

System Clock = 50 MHz (with

 

 

 

 

 

 

 

 

 

PLL)

 

 

 

 

 

 

 

 

Run mode 1

VDD25 = 2.50 V

48

pendinga

100

pendinga

0

pendinga

mA

 

(SRAM loop)

Code= while(1){} executed in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

Peripherals = All ON

 

 

 

 

 

 

 

 

 

System Clock = 50 MHz (with

 

 

 

 

 

 

 

 

 

PLL)

 

 

 

 

 

 

 

 

Run mode 2

VDD25 = 2.50 V

5

pendinga

45

pendinga

0

pendinga

mA

 

(SRAM loop)

Code= while(1){} executed in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

Peripherals = All OFF

 

 

 

 

 

 

 

 

 

System Clock = 50 MHz (with

 

 

 

 

 

 

 

 

 

PLL)

 

 

 

 

 

 

 

IDD_SLEEP

Sleep mode

VDD25 = 2.50 V

5

pendinga

16

pendinga

0

pendinga

mA

 

 

Peripherals = All OFF

 

 

 

 

 

 

 

 

 

System Clock = 50 MHz (with

 

 

 

 

 

 

 

 

 

PLL)

 

 

 

 

 

 

 

IDD_DEEPSLEEP

Deep-Sleep

LDO = 2.25 V

4.6

pendinga

0.21

pendinga

0

pendinga

mA

 

mode

Peripherals = All OFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Clock = IOSC30KHZ/64

 

 

 

 

 

 

 

IDD_HIBERNATE

Hibernate

VBAT = 3.0 V

0

0

0

0

16

pendinga

µA

 

mode

VDD = 0 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD25 = 0 V

VDDA = 0 V

VDDPHY = 0 V

Peripherals = All OFF

System Clock = OFF

Hibernate Module = 32 kHz

a. Pending characterization completion.

November 16, 2008

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Preliminary

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