Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
БЭМЗ полищук доки / Склад / Datasheet_LM3S6965.pdf
Скачиваний:
10
Добавлен:
21.12.2020
Размер:
6.13 Mб
Скачать

Quadrature Encoder Interface (QEI)

Write the QEICTL register with the value of 0x0000.0018.

Write the QEIMAXPOS register with the value of 0x0000.0F9F.

5.Enable the quadrature encoder by setting bit 0 of the QEICTL register.

6.Delay for some time.

7.Read the encoder position by reading the QEIPOS register value.

19.4Register Map

Table 19-1 on page 526 lists the QEI registers. The offset listed is a hexadecimal increment to the register’s address, relative to the module’s base address:

QEI0: 0x4002.C000

QEI1: 0x4002.D000

Table 19-1. QEI Register Map

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x000

QEICTL

R/W

0x0000.0000

QEI Control

527

0x004

QEISTAT

RO

0x0000.0000

QEI Status

529

0x008

QEIPOS

R/W

0x0000.0000

QEI Position

530

0x00C

QEIMAXPOS

R/W

0x0000.0000

QEI Maximum Position

531

0x010

QEILOAD

R/W

0x0000.0000

QEI Timer Load

532

0x014

QEITIME

RO

0x0000.0000

QEI Timer

533

0x018

QEICOUNT

RO

0x0000.0000

QEI Velocity Counter

534

0x01C

QEISPEED

RO

0x0000.0000

QEI Velocity

535

0x020

QEIINTEN

R/W

0x0000.0000

QEI Interrupt Enable

536

0x024

QEIRIS

RO

0x0000.0000

QEI Raw Interrupt Status

537

0x028

QEIISC

R/W1C

0x0000.0000

QEI Interrupt Status and Clear

538

19.5Register Descriptions

The remainder of this section lists and describes the QEI registers, in numerical order by address offset.

526

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 1: QEI Control (QEICTL), offset 0x000

This register contains the configuration of the QEI module. Separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset mode, and velocity predivider are all set via this register.

QEI Control (QEICTL)

QEI0 base: 0x4002.C000

QEI1 base: 0x4002.D000

Offset 0x000

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

STALLEN

INVI

INVB

INVA

 

VelDiv

 

VelEn

ResMode CapMode

SigMode

Swap

Enable

Type

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:13

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

12

STALLEN

R/W

0

Stall QEI

 

 

 

 

When set, the QEI stalls when the microcontroller asserts Halt.

11

INVI

R/W

0

Invert Index Pulse

 

 

 

 

When set , the input Index Pulse is inverted.

10

INVB

R/W

0

Invert PhB

 

 

 

 

When set, the PhB input is inverted.

9

INVA

R/W

0

Invert PhA

 

 

 

 

When set, the PhA input is inverted.

8:6

VelDiv

R/W

0x0

Predivide Velocity

 

 

 

 

A predivider of the input quadrature pulses before being applied to the

 

 

 

 

QEICOUNT accumulator. This field can be set to the following values:

Value Predivider

0x0 ÷1

0x1 ÷2

0x2 ÷4

0x3 ÷8

0x4 ÷16

0x5 ÷32

0x6 ÷64

0x7 ÷128

November 16, 2008

527

Preliminary

Quadrature Encoder Interface (QEI)

Bit/Field

Name

Type

Reset

Description

5

VelEn

R/W

0

Capture Velocity

 

 

 

 

When set, enables capture of the velocity of the quadrature encoder.

4

ResMode

R/W

0

Reset Mode

 

 

 

 

The Reset mode for the position counter. When 0, the position counter

 

 

 

 

is reset when it reaches the maximum; when 1, the position counter is

 

 

 

 

reset when the index pulse is captured.

3

CapMode

R/W

0

Capture Mode

 

 

 

 

The Capture mode defines the phase edges that are counted in the

 

 

 

 

position. When 0, only the PhA edges are counted; when 1, the PhA

 

 

 

 

and PhB edges are counted, providing twice the positional resolution

 

 

 

 

but half the range.

2

SigMode

R/W

0

Signal Mode

 

 

 

 

When 1, the PhA and PhB signals are clock and direction; when 0, they

 

 

 

 

are quadrature phase signals.

1

Swap

R/W

0

Swap Signals

 

 

 

 

Swaps the PhA and PhB signals.

0

Enable

R/W

0

Enable QEI

 

 

 

 

Enables the quadrature encoder module.

528

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 2: QEI Status (QEISTAT), offset 0x004

This register provides status about the operation of the QEI module.

QEI Status (QEISTAT)

QEI0 base: 0x4002.C000

QEI1 base: 0x4002.D000

Offset 0x004

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

Direction

Error

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

Direction

RO

0

Direction of Rotation

 

 

 

 

Indicates the direction the encoder is rotating.

 

 

 

 

The Direction values are defined as follows:

 

 

 

 

Value Description

0 Forward rotation

1 Reverse rotation

0

Error

RO

0

Error Detected

Indicates that an error was detected in the gray code sequence (that is, both signals changing at the same time).

November 16, 2008

529

Preliminary

Соседние файлы в папке Склад