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LM3S6965 Microcontroller

Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068

Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8

Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8

The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1 signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see page 520), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by the value in the PWM0DBFALL register (see page 521). In a similar manner, PWM2 and PWM3 are produced from the PWM1A and PWM1B signals, and PWM4 and PWM5 are produced from the PWM2A and PWM2B signals.

PWM0 Dead-Band Control (PWM0DBCTL)

Base 0x4002.8000

Offset 0x068

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Enable

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:1

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

0

Enable

R/W

0

Dead-Band Generator Enable

 

 

 

 

When set, the dead-band generator inserts dead bands into the output

 

 

 

 

signals; when clear, it simply passes the PWM signals through.

November 16, 2008

519

Preliminary

Pulse Width Modulator (PWM)

Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C

Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC

Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC

The PWM0DBRISE registercontainsthenumberofclocktickstodelaytherisingedgeofthe PWM0A signal when generating the PWM0 signal. If the dead-band generator is disabled through the PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire High time of the signal, resulting in no High time on the output. Care must be taken to ensure that the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge delayed.

PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)

Base 0x4002.8000

Offset 0x06C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

 

 

 

 

 

RiseDelay

 

 

 

 

 

Type

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:12

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

11:0

RiseDelay

R/W

0

Dead-Band Rise Delay

 

 

 

 

The number of clock ticks to delay the rising edge.

520

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070

Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0

Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0

The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time ontheoutput. CaremustbetakentoensurethattheinputLowtimealwaysexceedsthefalling-edge delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed and PWM5 is produced from PWM2A with its falling edge delayed.

PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)

Base 0x4002.8000

Offset 0x070

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

 

 

 

 

 

FallDelay

 

 

 

 

 

Type

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:12

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

11:0

FallDelay

R/W

0x00

Dead-Band Fall Delay

 

 

 

 

The number of clock ticks to delay the falling edge.

November 16, 2008

521

Preliminary

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