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LM3S6965 Microcontroller

Register 22: PWM0 Load (PWM0LOAD), offset 0x050

Register 23: PWM1 Load (PWM1LOAD), offset 0x090

Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0

These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator0block,andsoon). Basedonthecountermode,eitherthisvalueisloadedintothecounter afteritreacheszero,oritisthelimitofup-countingafterwhichthecounterdecrementsbacktozero.

If the Load Value Update mode is immediate, this value is used the next time the counter reaches zero;ifthemodeissynchronous,itisusedthenexttimethecounterreacheszeroafterasynchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 494). If this register is re-written before the actual update occurs, the previous value is never used and is lost.

PWM0 Load (PWM0LOAD)

Base 0x4002.8000

Offset 0x050

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Load

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

Load

R/W

0

Counter Load Value

 

 

 

 

The counter load value.

November 16, 2008

509

Preliminary

Pulse Width Modulator (PWM)

Register 25: PWM0 Counter (PWM0COUNT), offset 0x054

Register 26: PWM1 Counter (PWM1COUNT), offset 0x094

Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4

These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on). When this value matches the load register, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see page 513 and page 516) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see page 505). A pulse with the same capabilities is generated when this value is zero.

PWM0 Counter (PWM0COUNT)

Base 0x4002.8000

Offset 0x054

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Count

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

Count

RO

0x00

Counter Value

 

 

 

 

The current value of the counter.

510

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058

Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098

Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8

These registers contain a value to be compared against the counter (PWM0CMPA controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register (see page 509), then no pulse is ever output.

IfthecomparatorAupdatemodeisimmediate(basedonthe CmpAUpd bitinthe PWMnCTL register), this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is synchronous,itisusedthenexttimethecounterreacheszeroafterasynchronousupdatehasbeen requested through the PWM Master Control (PWMCTL) register (see page 494). If this register is rewritten before the actual update occurs, the previous value is never used and is lost.

PWM0 Compare A (PWM0CMPA)

Base 0x4002.8000

Offset 0x058

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

CompA

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

CompA

R/W

0x00

Comparator A Value

 

 

 

 

The value to be compared against the counter.

November 16, 2008

511

Preliminary

Pulse Width Modulator (PWM)

Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C

Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C

Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC

These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register, no pulse is ever output.

IfthecomparatorBupdatemodeisimmediate(basedonthe CmpBUpd bitinthe PWMnCTL register), this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is synchronous,itisusedthenexttimethecounterreacheszeroafterasynchronousupdatehasbeen requested through the PWM Master Control (PWMCTL) register (see page 494). If this register is rewritten before the actual update occurs, the previous value is never used and is lost.

PWM0 Compare B (PWM0CMPB)

Base 0x4002.8000

Offset 0x05C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

CompB

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

CompB

R/W

0x00

Comparator B Value

 

 

 

 

The value to be compared against the counter.

512

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0

Theseregisterscontrolthegenerationofthe PWMnA signalbasedontheloadandzerooutputpulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.

The PWM0GENA registercontrolsgenerationofthe PWM0A signal; PWM1GENA,the PWM1A signal; and PWM2GENA, the PWM2A signal.

If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare A action is taken and the compare B action is ignored.

PWM0 Generator A Control (PWM0GENA)

Base 0x4002.8000

Offset 0x060

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

ActCmpBD

ActCmpBU

ActCmpAD

ActCmpAU

ActLoad

ActZero

Type

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:12

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

11:10

ActCmpBD

R/W

0x0

Action for Comparator B Down

 

 

 

 

The action to be taken when the counter matches comparator B while

 

 

 

 

counting down.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1 Invert the output signal.

0x2 Set the output signal to 0.

0x3 Set the output signal to 1.

November 16, 2008

513

Preliminary

Pulse Width Modulator (PWM)

Bit/Field

Name

Type

Reset

Description

9:8

ActCmpBU

R/W

0x0

Action for Comparator B Up

 

 

 

 

The action to be taken when the counter matches comparator B while

 

 

 

 

counting up. Occurs only when the Mode bit in the PWMnCTL register

 

 

 

 

(see page 503) is set to 1.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

7:6

ActCmpAD

R/W

0x0

Action for Comparator A Down

 

 

 

 

The action to be taken when the counter matches comparator A while

 

 

 

 

counting down.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

5:4

ActCmpAU

R/W

0x0

Action for Comparator A Up

 

 

 

 

The action to be taken when the counter matches comparator A while

 

 

 

 

counting up. Occurs only when the Mode bit in the PWMnCTL register

 

 

 

 

is set to 1.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

3:2

ActLoad

R/W

0x0

Action for Counter=Load

 

 

 

 

The action to be taken when the counter matches the load value.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

514

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

1:0

ActZero

R/W

0x0

Action for Counter=0

 

 

 

 

The action to be taken when the counter is zero.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

November 16, 2008

515

Preliminary

Pulse Width Modulator (PWM)

Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4

Theseregisterscontrolthegenerationofthe PWMnB signalbasedontheloadandzerooutputpulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced.

The PWM0GENB registercontrolsgenerationofthe PWM0B signal; PWM1GENB,the PWM1B signal; and PWM2GENB, the PWM2B signal.

If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare B action is taken and the compare A action is ignored.

PWM0 Generator B Control (PWM0GENB)

Base 0x4002.8000

Offset 0x064

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

ActCmpBD

ActCmpBU

ActCmpAD

ActCmpAU

ActLoad

ActZero

Type

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:12

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

11:10

ActCmpBD

R/W

0x0

Action for Comparator B Down

 

 

 

 

The action to be taken when the counter matches comparator B while

 

 

 

 

counting down.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1 Invert the output signal.

0x2 Set the output signal to 0.

0x3 Set the output signal to 1.

516

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

9:8

ActCmpBU

R/W

0x0

Action for Comparator B Up

 

 

 

 

The action to be taken when the counter matches comparator B while

 

 

 

 

counting up. Occurs only when the Mode bit in the PWMnCTL register

 

 

 

 

is set to 1.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

7:6

ActCmpAD

R/W

0x0

Action for Comparator A Down

 

 

 

 

The action to be taken when the counter matches comparator A while

 

 

 

 

counting down.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

5:4

ActCmpAU

R/W

0x0

Action for Comparator A Up

 

 

 

 

The action to be taken when the counter matches comparator A while

 

 

 

 

counting up. Occurs only when the Mode bit in the PWMnCTL register

 

 

 

 

is set to 1.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

3:2

ActLoad

R/W

0x0

Action for Counter=Load

 

 

 

 

The action to be taken when the counter matches the load value.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

November 16, 2008

517

Preliminary

Pulse Width Modulator (PWM)

Bit/Field

Name

Type

Reset

Description

1:0

ActZero

R/W

0x0

Action for Counter=0

 

 

 

 

The action to be taken when the counter is 0.

 

 

 

 

The table below defines the effect of the event on the output signal.

 

 

 

 

Value

Description

 

 

 

 

0x0

Do nothing.

 

 

 

 

0x1

Invert the output signal.

 

 

 

 

0x2

Set the output signal to 0.

 

 

 

 

0x3

Set the output signal to 1.

518

November 16, 2008

Preliminary

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